verilog

本文将介绍Verilog语言的基础知识及其在FPGA开发中的应用,包括如何使用Verilog进行逻辑设计、综合与仿真,以及FPGA开发流程的概述。
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module gps_decoder(
    input rx_clk,
    input rx_data,
    input reset,
    
    output [7:0] latitude,
    output [7:0] longitude,
    output [7:0] altitude,
    output [7:0] speed,
    output [7:0] heading,
    output [7:0] utc_hour,
    output [7:0] utc_min,
    output [7:0] utc_sec,
    output [7:0] sat_count,
    output [7:0] hdop
    );
    
    /*
    *定义常量
    */
    localparam BYTE_COUNT = 66;  //NMEA消息的字节数
    localparam DATA_START = 8;   //数据开始的字节
    
    /*
    *定义寄存器
    */
    reg [7:0] buffer [BYTE_COUNT-1:0];
    reg [7:0] buffer_pointer = 0;
    reg ready = 0;
    reg process = 0;
    
    /*
    *定义部分GPS消息的字段
    */
    reg [2:0] message_id;
    reg [7:0] utc_time[3];
    reg [7:0] latitude_b[3];
    reg [7:0] longitude_b[3];
    reg [7:0] altitude_b[3];
    reg [7:0] speed_b[3];
    reg [7:0] heading_b[3];
    reg [7:0] sat_count_b;
    reg [7:0] hdop_b[2];
    
    /*
    *状态机状态
    */
    localparam IDLE = 0;
    localparam RX = 1;
    localparam PARSE = 2;
    localparam ERROR = 3;
    reg [1:0] state = IDLE;
    
    
    /*
    *等待启动
    */
    always @(posedge rx_clk) begin
        if (reset) begin
            state <= IDLE;
            buffer_pointer <= 0;
            ready <= 0;
            process <= 0;
        end else begin
            case(state)
                IDLE: begin
                    if (rx_data == $8A) begin
                        buffer_pointer <= 0;
                        state <= RX;
                    end
                end
                RX: begin
                    buffer[buffer_pointer] <= rx_data;
                    buffer_pointer <= buffer_pointer+1;
                    state <= (buffer_pointer == BYTE_COUNT) ? PARSE : RX;
                end
                PARSE: begin
                    ready <= 1;
                    state <= IDLE;
                    process <= 1;
                end
                ERROR: begin
                    state <= IDLE;
                    buffer_pointer <= 0;
                end
            endcase
        end
    end
     /*
    *数据解析
    */
    always @(posedge rx_clk) begin
        if (process) begin
            process <= 0;
            if (buffer[3] == 'R' && buffer[4] == 'M' && buffer[5] == 'C') begin
                message_id = 0;
                sat_count_b = "00000000";
            end else if (buffer[3] == 'G' && buffer[4] == 'G' && buffer[5] == 'A') begin
                message_id = 1;
                sat_count_b = buffer[8];
            end else if (buffer[3] == 'G' && buffer[4] == 'L' && buffer[5] == 'L') begin
                message_id = 2;
                sat_count_b = buffer[8];
            end else if (buffer[3] == 'G' && buffer[4] == 'S' && buffer[5] == 'A') begin
                message_id = 3;
            end else if (buffer[3] == 'G' && buffer[4] == 'S' && buffer[5] == 'V') begin
                message_id = 4;
            end else if (buffer[3] == 'G' && buffer[4] == 'S' && buffer[5] == 'T') begin
                message_id = 5;
            end else begin
                message_id = -1;
            end
            
            case(message_id)
                0: begin
                    //提取速度和航向信息
                    speed_b[0] = buffer[DATA_START+4];
                    speed_b[1] = buffer[DATA_START+5];
                    heading_b[0] = buffer[DATA_START+6];
                    heading_b[1] = buffer[DATA_START+7];
                end
                1, 2: begin
                    //提取UTC时间,纬度,经度,海拔信息
                    utc_time[0] = buffer[DATA_START];
                    utc_time[1] = buffer[DATA_START+1];
                    utc_time[2] = buffer[DATA_START+2];
                    latitude_b[0] = buffer[DATA_START+2];
                    latitude_b[1] = buffer[DATA_START+3];
                    latitude_b[2] = buffer[DATA_START+4];
                    longitude_b[0] = buffer[DATA_START+5];
                    longitude_b[1] = buffer[DATA_START+6];
                    longitude_b[2] = buffer[DATA_START+7];
                    altitude_b[0] = buffer[DATA_START+8];
                    altitude_b[1] = buffer[DATA_START+9];
         
odule GPS ( //////////////////// Clock Input //////////////////// CLOCK_24, // 24 MHz CLOCK_27, // 27 MHz CLOCK_50, // 50 MHz EXT_CLOCK, // External Clock //////////////////// Push Button //////////////////// KEY, // Pushbutton[3:0] //////////////////// DPDT Switch //////////////////// SW, // Toggle Switch[9:0] //////////////////// 7-SEG Dispaly //////////////////// HEX0, // Seven Segment Digit 0 HEX1, // Seven Segment Digit 1 HEX2, // Seven Segment Digit 2 HEX3, // Seven Segment Digit 3 //////////////////////// LED //////////////////////// LEDG, // LED Green[7:0] LEDR, // LED Red[9:0] //////////////////////// UART //////////////////////// UART_TXD, // UART Transmitter UART_RXD, // UART Receiver ///////////////////// SDRAM Interface //////////////// DRAM_DQ, // SDRAM Data bus 16 Bits DRAM_ADDR, // SDRAM Address bus 12 Bits DRAM_LDQM, // SDRAM Low-byte Data Mask DRAM_UDQM, // SDRAM High-byte Data Mask DRAM_WE_N, // SDRAM Write Enable DRAM_CAS_N, // SDRAM Column Address Strobe DRAM_RAS_N, // SDRAM Row Address Strobe DRAM_CS_N, // SDRAM Chip Select DRAM_BA_0, // SDRAM Bank Address 0 DRAM_BA_1, // SDRAM Bank Address 0 DRAM_CLK, // SDRAM Clock DRAM_CKE, // SDRAM Clock Enable //////////////////// Flash Interface //////////////// FL_DQ, // FLASH Data bus 8 Bits FL_ADDR, // FLASH Address bus 22 Bits FL_WE_N, // FLASH Write Enable FL_RST_N, // FLASH Reset FL_OE_N, // FLASH Output Enable FL_CE_N, // FLASH Chip Enable //////////////////// SRAM Interface //////////////// SRAM_DQ, // SRAM Data bus 16 Bits SRAM_ADDR, // SRAM Address bus 18 Bits SRAM_UB_N, // SRAM High-byte Data Mask SRAM_LB_N, // SRAM Low-byte Data Mask SRAM_WE_N, // SRAM Write Enable SRAM_CE_N, // SRAM Chip Enable SRAM_OE_N, // SRAM Output Enable //////////////////// SD_Card Interface //////////////// SD_DAT, // SD Card Data SD_DAT3, // SD Card Data 3 SD_CMD, // SD Card Command Signal SD_CLK, // SD Card Clock //////////////////// USB JTAG link //////////////////// TDI, // CPLD -> FPGA (data in) TCK, // CPLD -> FPGA (clk) TCS, // CPLD -> FPGA (CS) TDO, // FPGA -> CPLD (data out) //////////////////// I2C //////////////////////////// I2C_SDAT, // I2C Data I2C_SCLK, // I2C Clock //////////////////// PS2 //////////////////////////// PS2_DAT, // PS2 Data PS2_CLK, // PS2 Clock //////////////////// VGA //////////////////////////// VGA_HS, // VGA H_SYNC
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