S5PV210的I2C通信

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S5PV210 I2C总线接口

S5PV210 RISC(精简指令集)式微处理器支持四个多控制I2C总线串行接口。为了在总线主设备和连接了I2C总线的外部设备（从设备）之间传输数据信息，需要用到一条专用的串行数据线SDA和一条串行时钟线SCL。SDA和SCL都是双向通信的。

 

在多控制I2C总线主设备模式中，多种S5PV210 RISC微处理器接收从设备串行数据或者发送串行数据到从设备。S5PV210主控制器在I2C总线上启动数据或终止数据传送。在S5PV210中I2C总线使用一个标准总线分配程序。

 

为了控制I2C总线主设备操作，需要对它的下列寄存器进行设置：

I2C总线主设备控制寄存器——I2CCON;

I2C总线主设备控制状态寄存器——I2CSTAT;

I2C总线主设备发送\接收数据移位寄存器——I2CDS；

I2C总线主设备地址寄存器——I2CADD;

 

如果I2C总线被释放（空闲状态），串行数据线（SDA）和串行时钟线（SCL）都应该是高电平。当SDA电平出现由高向低的转变，则意为开始一个启动过程；

当SCL电平稳定保持在高电平而SDA的电平出现由低向高的转变，则意为开始一个停止过程；

 

主设备总是产生启动和停止的过程；在开始启动过程后，数据字节地址中的7个位（bit[1]-bit[7]）会被传送到串行数据线SDA上，通过它能够确定总线主设备所选的通信从设备；而第8位（bit[0]）则决定是读或是写。

 

每个数据字节放到串行数据线上都必须是完整的八位。在总线传输操作中，不限制发送或接收的字节数量；数据总是先发送高位(即MSB)，每发送一位都需要立即跟上一个响应（ACK）位来反馈。

翻译原文来源于S5PV210数据手册：

S5PV210 IIC-BUS INTERFACE 

The S5PV210 RISC microprocessor supports four multi-master I2C bus serial interfaces. To carry information between bus masters and peripheral devices connected to the I2C bus, a dedicated Serial Data Line (SDA) and an Serial Clock Line (SCL) is used. Both SDA and SCL lines are bi-directional. 

In multi-master I2C-bus mode, multiple S5PV210 RISC microprocessors receive or transmit serial data to or from slave devices. The master S5PV210 initiates and terminates a data transfer over the I2C bus. The I2C bus in the S5PV210 uses a standard bus arbitration procedure. 

To control multi-master I2C-bus operations, values must be written to the following registers: 

•Multi-master I2C-bus control register- I2CCON 

•Multi-master I2C-bus control/status register- I2CSTAT 

•Multi-master I2C-bus Tx/Rx data shift register- I2CDS 

•Multi-master I2C-bus address register- I2CADD 

If the I2C-bus is free, both SDA and SCL lines should be both at High level. A High-to-Low transition of SDA initiates a Start condition. A Low-to-High transition of SDA initiates a Stop condition while SCL remains steady at High Level. 

The master device always generates Start and Stop conditions. First 7-bit address value in the data byte that is transferred via SDA line after the Start condition has been initiated, can determine the slave device which the bus master device has selected. The 8th bit determines the direction of the transfer (read or write).

  Every data byte put onto the SDA line should be eight bits in total. There is no limit to send or receive bytes during the bus transfer operation. Data is always sent from most-significant bit (MSB) first, and every byte should be immediately followed by acknowledge (ACK) bit.