这里主要做个实验,实验一下switch语句和when elsewhen语句。
package simple
import chisel3._
import chisel3.util._
class aWordSel (size : Int ) extends Module {
val io = IO(new Bundle {
val sel = Input( UInt(2.W))
val in = Input (UInt((size*4).W ))
val out = Output ( UInt(size.W ) )
})
val word0 = io.in( (size-1) , 0 )
val word1 = io.in( (size*2-1) , size )
val word2 = io.in( (size*3-1) , (size*2) )
val word3 = io.in( (size*4-1) , (size*3) )
io.out := 0.U(size.W)
val r0 = Wire(UInt(size.W))
r0 := 0.U
switch (io.sel){
is (0.U) { r0 := word0 }
is (1.U) { r0 := word1 }
is (2.U) { r0 := word2 }
is (3.U) { r0 := word3 }
}
val r1 = Wire(UInt(size.W))
r1 :=0.U ;
when (io.sel === 0.U(2.W)){
r1 := word0
} .elsewhen(io.sel ===1.U){
r1 := word1
} .elsewhen(io.sel ===2.U){
r1 := word2
//} .elsewhen(io.sel ===3.U){
} .otherwise {
r1 := word3
}
io.out := r0
}
object WordSel extends App{
println("Generating the aWordSel hardware ")
chisel3.Driver.execute(Array("--target-dir","generated"),()=>new aWordSel(128))
}
这里注意使用switch要import chisel3.util._
对比一下生成的verilog 都是说冲选择的方式,没有差别。