asip designer错误及解决方案

错误1

ERROR: incomplete register transfer(s) for following instruction(s):

Please check that the outputs of the following statements and assignments are connected to registers or memories, whenever they are enabled. (inports, outports, and - except for the compiler - transitories with hw_init are also OK.) Please also verify the timing of these connections, in particular read/write timing for pipeline registers and transitories.

解决
asipdesigner中的opn中，操作必须从storage开始到storage结束。如果数据传递中间出现分支语句，可能会由于分支语句没有补全而出现以上问题。

• switch和if分支必须补全才能避免以上问题。
• 如果逻辑中只是条件执行（即只有if没有else），那么这种逻辑只能用guard条件执行来实现。

注：给transitory加hw_init可以掩盖该错误，但是最好不要用，因为nml-manual解释hw_init用法如下：

An initial value of a transitory expresses that the transitory is initialized at the beginning of every cycle with that value. During some cycle, the initial value can be overwritten at most once. Such a transitory has always a meaningful value, also when it not written in some cycle. This implies that a valid instruction can start from and end in such a transitory, instead of a static storage. These transitories are typically used to interact with the processor controller modeled outside of nML。