总线架构性能评估--ARM的解决之道

ARM is offering one answer: an IP block that can be inserted into the RTL or transaction-level model of a design and used during software simulation or hardware emulation to collect statistics on dataflows. This data is far more compact than actual recordings or vector lists. The block can then be used to generate pseudorandom traffic streams based on the statistics.

Using this verification IP, designers can set up their simulation model of the chip for suspected traffic-corner cases. They can then use the traffic-analysis IP blocks to profile the traffic flowing between blocks in the simulation during runs. The statistical profiles can then be used, at either the transaction or cycle-accurate level and apparently also with RTL, to examine the operation of the chip over a range of interconnect scales, topologies, buffer sizes, and the like.

In effect, the IP blocks allow designers to apply traditional functional verification techniques of pseudorandom vector testing not merely to the logical correctness of the interconnect, but also to its dynamic performance. It is an important step in dealing with the emergence of on-chip buses and links as a critical feature in complex SOCs.