1. 时序仿真图
2。减计数器
3.数码管显示
4.设置时间
5.译码输出
顶层文件
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity total is
port(
clk1,start1,load1:in std_logic;
k1:in std_logic_vector(9 downto 0);
REV1,RUN1,PAUSE1:out std_logic;
h,i,j,k,l,m,n,o,p,q,r,s,t,u:out std_logic
-- time_is_end:out std_logic
);
end entity total;
architecture one of total is
component counter --计数器
port(clk,start:in std_logic;
k:in STD_LOGIC_VECTOR(7 downto 0);
time_remain:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
time_is_up:out std_logic
);
end component;
component decoder--译码器
port( Q1,Q2: in std_logic;
REV,RUN,PAUSE: out std_logic );
end component;
component settime --设置时间
port(load:in std_logic;
k:in std_logic_vector(9 downto 0);
o:out std_logic_vector(7 downto 0)
);
end component;
component shixu --时序
port(cp,en,rd:in std_logic;
q1,q2:out std_logic--00为停机,10为正转,01为反转
);
end component;
component showtime--