Lint 检查： Width Mismatch & Overflow

///
module test_add();

input   [2:0] a1;
input   [3:0] b1;
output  [3:0] c1;

input   [2:0] a2;
input   [3:0] b2;
output  [3:0] c2;

input   [2:0] a3;
input   [3:0] b3;
output        c3;

input         sel;
input   [2:0] a4;
input   [3:0] b4;
output  [3:0] c4;

input   [2:0] a5;
input   [2:0] b5;
output  [1:0] c5;

input   [2:0] a6;
input   [2:0] b6;
output  [3:0] c6;

assign c1 = a1 + b1;         // + unsigned  width mismatch and overflow
assign c2 = a2 + b2;         // + signed    width mismatch and overflow
assign c3 = a3 > b3;         // >           width mismatch
assign c4 = sel ? a4 : b4;   // ?           width mismatch
assign c5 = a5 + b5;         // =           LHS < RHS 
assign c6 = a6 + b6;         // =           LHS > RHS 

// Bit width mismatch is not a simulation or synthesis error, because Verilog
// standard has defined how to handle these situations: 
//    1) when and how to complete bit width 
//    2) when and how to drop bit width
// Simulation and Synthesis tool will simulate or synthesize RTL code as the 
// Verilog standard tells them, so netlist simulation result will match RTL 
// simulation result.
//
// Bit width mismatch is reported because it may be a coding miss or design
// miss. If these misses are covered by simulation test cases, they can be 
// discovered and fixed, otherwise they can cause chip fail. In other words
// width mismatch check can help find some bugs that may not be covered by
// simulation test cases.
//
// So bit width mismatch should be confirmed by designer other than verifier
// to make sure that bit witdh of operators are intentionally designed and
// the mismatch between them will not cause any functional problem.

endmodule