format display on systemverilog

Format specifications:

Argument Description
%h or %H
%x or %X Display in hexadecimal format
%d or %D Display in decimal format
%o or %O Display in octal format
%b or %B Display in binary format
%c or %C Display in ASCII character format
%l or %L Display library binding information
%v or %V Display net signal strength
%m or %M Display hierarchical name
%p or %P Display as an assignment pattern
%s or %S Display as a string
%t or %T Display in current time format
%u or %U Unformatted 2 value data
%z or %Z Unformatted 4 value data

So the example about display enum
module top;
typedef enum {ON, OFF} switch_e;
switch_e s;
initial begin
s=ON;
$display(“the enum of switch_e is %p.”,s);
endmodule : top

resule: the enum of switch_e is ON.