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Vinson_Yin
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define to string in systemverilog
有时候我们需要打印macro,这就需要把define的值转成string类型。方法二:“``HIER_TB_TOP``”原创 2024-03-25 11:55:12 · 207 阅读 · 0 评论 -
systemverilog functional coverage with argument
covergroup cg_multi_layer(ref int layer0_index, int layer1_index, input int size); cp_layer0: coverpoint layer0_index { bins id[]={[0:size]}; } cp_layer1: coverpoint layer1_index { bins id[]={[0:size]}; } ...原创 2021-08-17 17:34:30 · 140 阅读 · 0 评论 -
SystemVerilog file operations
一. open,close, writefwrite(fd, data);int fd;fd = $fopen("file", "w”);$fdisplay(fd,"%x", data);$fclose(fd);二. 判断文件是否存在如果文件open 为0,代表打开失败,否则成功三. 读取文件fd = fopen("file", "r");if (fd) begin // read successfule while($feof(fd)) begin $fg原创 2021-05-26 16:24:32 · 1314 阅读 · 0 评论 -
Add delay for Verilog
在verilog中添加delay推荐assign #5 y=~x; always @(a) y <= #5 ~a;Continuous assignment delayassign #5 y = ~x; OKBlocking assignment delayalways @(a) #5 y = ~a; LHSalways @(a) y = #5 ~a; RHSplacing delays on the LHS of blocking assignments...原创 2021-02-23 14:25:54 · 1600 阅读 · 0 评论 -
Systemverilog Interface Classes
interfac class 可以定义一系列pure functioninterface class resolve_listener; pure virtual function void new_resolve(arm_txn_resolve resolve);endclassclass 可以implement interface classclass 可以implement 多个interface classclass ordering_checker extends ar.原创 2021-02-20 15:14:35 · 587 阅读 · 0 评论 -
verilog X value 操作
三目运算符out = sel ? a: b;当sel = x,使用xcelium的情况如下case1: 当a != b时, out = x;case2: 当a==b时,out = a/b;位操作原创 2020-09-10 10:26:36 · 1532 阅读 · 0 评论 -
systemverilog string split
module test; function automatic void parse ( output string out [$], input string in, input string separator = ",", input bit drop_blank = 1 ); string val, min, max; bit fl...原创 2018-11-14 20:08:54 · 4010 阅读 · 0 评论 -
systemverilog dpi usage
How to Embed Systemverilog Interpreter using DPI-C?:https://stackoverflow.com/questions/29781428/how-to-embed-systemverilog-interpreter-using-dpi-c/46441794#46441794https://verificationacademy.com...原创 2018-10-10 22:05:10 · 548 阅读 · 0 评论 -
SystemVerilog dynamic constraint using decorator
systemverilog的constraint也支持decorator(dynamic constraint)class trans; rand bit [9:0] addr; constraint cons_addr { addr inside {[1:100]}; } virtual function void rprint(); this.randomize(); ...原创 2018-05-24 20:57:36 · 412 阅读 · 0 评论 -
systemverilog 在class中使用force
1.直接force某个值,比如0/1/a之类的,可以在class中直接force2.force某个变量的值,比如 force dut.timer=timer, 如果timer是一个动态变量的话,编译会报错“Class data is not allowed in non-procedural context.”,简单的解法是把timer定义成static类型3.如果2中不能简单定义成static类...原创 2018-04-29 11:19:43 · 9549 阅读 · 0 评论 -
good usage on systemverilog
再次细看uvm source code, 借此把里面用的很好的技巧和语法记录一下, 希望后面有精力陆续更新Macro参数传递1.使用参数1). `(一个shell 执行符, Esc 下面),猜是转义字符的功能,使其“” 与S分离开,使编译器认为S是传入值而非字符串2). ``(两个shell 执行符, Esc 下面),这种偏多了,保留参数S的值`define m_uv原创 2016-12-03 10:48:16 · 755 阅读 · 0 评论 -
systemverilog 变量位宽表示方法
在systemverilog中有时候需要进行位操作,比如data[15:12](data[16-1:16-1-3]), 另外一种表示方法为:program automatic demo; bit [16:0] data; initial begin data = 16'h1234; $display("data = %0h", data); $disp原创 2016-11-15 22:05:16 · 9085 阅读 · 0 评论 -
systemverilog queue 的使用,如何判断元素是否存在
Queue: int queue[$] = {1,2,3}; int queue[$:256]; //A queue whose maximum size is 256 bits7.10.1 operator queue[0:$] //travel the queue7.10.3 methods function int size();原创 2016-10-18 23:01:39 · 16479 阅读 · 0 评论 -
systemverilog string match
需求: 在systemverilog 的string看是否存在某个字节或某段字符串其实请前辈说match也不算是sv的语法了,而且只IEEE中确实也没有该function, 不过可以实现上面所需,用的时候可能会受simulator 的影响。eg:program string_test; string str = "add16_rri"; initial begin原创 2016-09-28 22:29:53 · 4689 阅读 · 0 评论 -
string to enum in systemverilog
the syntax of ENUM enum {red, yellow, green } color; default of data type is “int”default data value is 0, or set the customized value by user, eg: enum {red = 1, yellow = 100, green=1000}原创 2016-05-28 16:58:25 · 892 阅读 · 0 评论 -
format display on systemverilog
Format specifications:Argument Description %h or %H %x or %X Display in hexadecimal format %d or %D Display in decimal format %o or %O Display in octal format %b or %B Display in binary format %原创 2016-05-13 20:55:38 · 1157 阅读 · 0 评论 -
system on systemverilog
systemform the IEEE: systemmakesacalltotheCfunctionsystem().system makes a call to the C function system(). system can be called as either a task or a function. When called as a function, it return原创 2016-05-13 20:50:32 · 428 阅读 · 0 评论