RV1126&RV1109 buildroot 增加GPIO测试程序

最新推荐文章于 2024-06-13 15:34:37 发布
最新推荐文章于 2024-06-13 15:34:37 发布
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分类专栏： RV1109
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本文链接：https://blog.csdn.net/pebi2005/article/details/112316840
版权

补丁


Author: rockemd <rockemd2020@163.com>
Date:   Wed Jan 6 16:30:33 2021 +0800

    1.add iotest

diff --git a/buildroot/configs/rockchip_rv1126_rv1109_facial_gate_defconfig b/buildroot/configs/rockchip_rv1126_rv1109_facial_gate_defconfig
index 961d9ff..eb0d276 100755
--- a/buildroot/configs/rockchip_rv1126_rv1109_facial_gate_defconfig
+++ b/buildroot/configs/rockchip_rv1126_rv1109_facial_gate_defconfig
 BR2_PACKAGE_CAMERA_ENGINE_RKAIQ_RKISP_DEMO=y
 BR2_PACKAGE_IPC_DAEMON=y
 BR2_PACKAGE_CALLFUNIPC=y
@@ -90,5 +90,6 @@ BR2_PACKAGE_NGINX_DEBUG=y
 BR2_PACKAGE_NGINX_RTMP=y
 # BR2_PACKAGE_NTP_NTPD is not set
 BR2_PACKAGE_APP_UARTTEST=y
+BR2_PACKAGE_APP_IOTEST=y
 BR2_PACKAGE_APP_DWUART=y
 BR2_PACKAGE_PYTHON3=y
diff --git a/buildroot/package/rockchip/Config.in b/buildroot/package/rockchip/Config.in
index 9918426..885aedf 100755
--- a/buildroot/package/rockchip/Config.in
+++ b/buildroot/package/rockchip/Config.in
@@ -256,5 +256,6 @@ source "package/rockchip/pcba_adb_test/Config.in"
 source "package/rockchip/camera_factory_test_server/Config.in"
 source "package/rockchip/app-uarttest/Config.in"
 source "package/rockchip/app-dwuart/Config.in"
+source "package/rockchip/app-iotest/Config.in"
 source "package/rockchip/thunderboot/Config.in"
 endif
diff --git a/buildroot/package/rockchip/app-iotest/Config.in b/buildroot/package/rockchip/app-iotest/Config.in
new file mode 100755
index 0000000..bc5d58a
--- /dev/null
+++ b/buildroot/package/rockchip/app-iotest/Config.in
@@ -0,0 +1,4 @@
+config BR2_PACKAGE_APP_IOTEST
+	bool "iotest"
+	help
+	  rockemd iotest demo
diff --git a/buildroot/package/rockchip/app-iotest/app-iotest.mk b/buildroot/package/rockchip/app-iotest/app-iotest.mk
new file mode 100755
index 0000000..75ea149
--- /dev/null
+++ b/buildroot/package/rockchip/app-iotest/app-iotest.mk
@@ -0,0 +1,28 @@
+#############################################################
+#
+# IOTEST
+#
+#############################################################
+ifeq ($(BR2_PACKAGE_APP_IOTEST), y)
+APP_IOTEST_VERSION = 1.0.0
+APP_IOTEST_SITE_METHOD:=local
+APP_IOTEST_SITE=$(TOPDIR)/../external/iotest
+APP_IOTEST_INSTALL_TARGET:=YES
+
+define APP_IOTEST_BUILD_CMDS
+    $(MAKE) CC="$(TARGET_CC)" LD="$(TARGET_LD)" -C $(@D) all
+endef
+
+define APP_IOTEST_INSTALL_TARGET_CMDS
+    $(INSTALL) -D -m 0755 $(@D)/getgpio $(TARGET_DIR)/bin
+    $(INSTALL) -D -m 0755 $(@D)/setgpio $(TARGET_DIR)/bin
+endef
+
+define APP_IOTEST_PERMISSIONS
+    /bin/getgpio f 4755 0 0 - - - - -
+    /bin/setgpio f 4755 0 0 - - - - -
+endef
+
+$(eval $(generic-package))
+
+endif
diff --git a/external/iotest/Makefile b/external/iotest/Makefile
new file mode 100755
index 0000000..751b88c
--- /dev/null
+++ b/external/iotest/Makefile
@@ -0,0 +1,15 @@
+all: getgpio setgpio
+
+getgpio: getgpio.o
+	$(CC) -o getgpio getgpio.o
+	
+setgpio: setgpio.o 
+	$(CC) -o setgpio setgpio.o
+
+clean:
+	rm -rf *.o
+	rm -rf getgpio setgpio
+
+install:
+	$(INSTALL) -D -m 0755 getgpio $(TARGET_DIR)/bin
+	$(INSTALL) -D -m 0755 setgpio $(TARGET_DIR)/bin
diff --git a/external/iotest/getgpio.c b/external/iotest/getgpio.c
new file mode 100755
index 0000000..a3bb157
--- /dev/null
+++ b/external/iotest/getgpio.c
@@ -0,0 +1,118 @@
+#include "rv11xx.h"
+
+
+int openGpioDev() 
+{
+    int ret=0;
+
+    fd = open("/dev/rockemd", O_RDWR);
+    if (fd < 0) {
+        ret=-1;
+    }
+    return ret;
+}
+
+int closeGpioDev() 
+{
+
+    int ret=0;
+    ret = close(fd);
+    if (fd < 0) {
+        ret=-1;
+    }
+    return ret;
+}
+
+int setGpioState(int num, int state) 
+{
+    int err=-1;
+    struct UserData userdata;
+    memset(&userdata,0x00, sizeof(userdata));
+    userdata.gpio=num;
+    userdata.state=state;
+
+    err = ioctl(fd, CMD_SET_GPIO, &userdata);
+    if(err<0){
+        err=-1;
+    }
+    return err;
+}
+
+int getGpioState(int num)
+{
+    int ret=-1;
+    struct UserData userdata;
+    memset(&userdata,0x00, sizeof(userdata));
+    userdata.gpio=num;
+
+    ret = ioctl(fd, CMD_GET_GPIO, &userdata);
+
+    return ret;
+}
+
+int releaseGpio(int num)
+{
+    int ret=-1;
+    struct UserData userdata;
+    memset(&userdata,0x00, sizeof(userdata));
+    userdata.gpio=num;
+    userdata.state=0;
+    ret = ioctl(fd, CMD_RELEASE_GPIO, &userdata);
+    return ret;
+}
+
+
+void main(int argc,char * argv[])
+{	
+	if(argc != 2) {
+		/*C =3 B =2 C5 = (3 -1 )*8+5 = 21*/
+		printf("************************************\n");
+		printf("    	GPIO_A0	=	 0				\n");
+		printf("    	GPIO_A1	=	 1				\n");
+		printf("    	GPIO_A2	=	 2				\n");
+		printf("    	GPIO_A3	=	 3				\n");
+		printf("    	GPIO_A4	=	 4				\n");
+		printf("    	GPIO_A5	=	 5				\n");
+		printf("    	GPIO_A6	=	 6				\n");
+		printf("    	GPIO_A7	=	 7				\n");
+		printf("    	GPIO_B0	=	 8				\n");
+		printf("    	GPIO_B1	=	 9				\n");
+		printf("    	GPIO_B2	=	 10				\n");
+		printf("    	GPIO_B3	=	 11				\n");
+		printf("    	GPIO_B4	=	 12				\n");
+		printf("    	GPIO_B5	=	 13				\n");
+		printf("    	GPIO_B6	=	 14				\n");
+		printf("    	GPIO_B7	=	 15				\n");
+		printf("    	GPIO_C0	=	 16				\n");
+		printf("    	GPIO_C1	=	 17				\n");
+		printf("    	GPIO_C2	=	 18				\n");
+		printf("    	GPIO_C3	=	 19				\n");
+		printf("    	GPIO_C4	=	 20				\n");
+		printf("    	GPIO_C5	=	 21				\n");
+		printf("    	GPIO_C6	=	 22				\n");
+		printf("    	GPIO_C7	=	 23				\n");
+		printf("    	GPIO_D0	=	 24				\n");
+		printf("    	GPIO_D1	=	 25				\n");
+		printf("    	GPIO_D2	=	 26				\n");
+		printf("    	GPIO_D3	=	 27				\n");
+		printf("    	GPIO_D4	=	 28				\n");
+		printf("    	GPIO_D5	=	 29				\n");
+		printf("    	GPIO_D6	=	 30				\n");
+		printf("    	GPIO_D7	=	 31				\n");
+		printf("(GPIO3_B5_d-->GPIO_BUTTON)=3*32+13=109 	\n");
+
+        printf("please input gpio number 	\n");
+        printf("    getgpio 109				\n");
+        printf("************************************\n");
+        return -1;
+    }
+	int a = atoi(argv[1]);
+	openGpioDev();
+	while(1)
+	{
+		int ret = getGpioState(a);
+		printf("====== %d =======\n", ret);
+		sleep(1);
+	}
+	closeGpioDev();
+}
diff --git a/external/iotest/rv11xx.h b/external/iotest/rv11xx.h
new file mode 100755
index 0000000..6ee8b49
--- /dev/null
+++ b/external/iotest/rv11xx.h
@@ -0,0 +1,349 @@
+#include <stdio.h>
+#include <math.h>
+#include <malloc.h>
+#include <sys/ioctl.h>
+#include <fcntl.h>
+
+#define CMD_GET_GPIO		0		//gpio_get_value
+#define CMD_SET_GPIO		1		//gpio_set_value
+#define CMD_RELEASE_GPIO 	2		//gpio_free
+
+struct UserData{
+    int gpio;
+    int state;
+};
+
+int fd=-1;
+
+#define RK_GPIO_BANK_OFFSET = 32;
+
+#define	GPIO_A0	=	    0;
+#define	GPIO_A1	=		1;
+#define	GPIO_A2	=		2;
+#define	GPIO_A3	=		3;
+#define	GPIO_A4	=		4;
+#define	GPIO_A5	=		5;
+#define	GPIO_A6	=		6;
+#define	GPIO_A7	=		7;
+#define	GPIO_B0	=		8;
+#define	GPIO_B1	=		9;
+#define	GPIO_B2	=		10;
+#define	GPIO_B3	=		11;
+#define	GPIO_B4	=		12;
+#define	GPIO_B5	=		13;
+#define	GPIO_B6	=		14;
+#define	GPIO_B7	=		15;
+#define	GPIO_C0	=		16;
+#define	GPIO_C1	=		17;
+#define	GPIO_C2	=		18;
+#define	GPIO_C3	=		19;
+#define	GPIO_C4	=		20;
+#define	GPIO_C5	=		21;
+#define	GPIO_C6	=		22;
+#define	GPIO_C7	=		23;
+#define	GPIO_D0	=		24;
+#define	GPIO_D1	=		25;
+#define	GPIO_D2	=		26;
+#define	GPIO_D3	=		27;
+#define	GPIO_D4	=		28;
+#define	GPIO_D5	=		29;
+#define	GPIO_D6	=		30;
+#define	GPIO_D7	=		31;
+//GPIO0
+#define RK30_PIN0_PA0 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_A0;
+#define RK30_PIN0_PA1 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_A1;
+#define RK30_PIN0_PA2 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_A2;
+#define RK30_PIN0_PA3 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_A3;
+#define RK30_PIN0_PA4 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_A4;
+#define RK30_PIN0_PA5 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_A5;
+#define RK30_PIN0_PA6 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_A6;
+#define RK30_PIN0_PA7 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_A7;
+#define RK30_PIN0_PB0 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_B0;
+#define RK30_PIN0_PB1 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_B1;
+#define RK30_PIN0_PB2 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_B2;
+#define RK30_PIN0_PB3 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_B3;
+#define RK30_PIN0_PB4 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_B4;
+#define RK30_PIN0_PB5 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_B5;
+#define RK30_PIN0_PB6 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_B6;
+#define RK30_PIN0_PB7 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_B7;
+#define RK30_PIN0_PC0 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_C0;
+#define RK30_PIN0_PC1 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_C1;
+#define RK30_PIN0_PC2 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_C2;
+#define RK30_PIN0_PC3 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_C3;
+#define RK30_PIN0_PC4 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_C4;
+#define RK30_PIN0_PC5 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_C5;
+#define RK30_PIN0_PC6 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_C6;
+#define RK30_PIN0_PC7 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_C7;
+#define RK30_PIN0_PD0 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_D0;
+#define RK30_PIN0_PD1 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_D1;
+#define RK30_PIN0_PD2 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_D2;
+#define RK30_PIN0_PD3 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_D3;
+#define RK30_PIN0_PD4 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_D4;
+#define RK30_PIN0_PD5 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_D5;
+#define RK30_PIN0_PD6 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_D6;
+#define RK30_PIN0_PD7 = (0 * RK_GPIO_BANK_OFFSET) + GPIO_D7;
+    //GPIO1
+#define RK30_PIN1_PA0 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_A0;
+#define RK30_PIN1_PA1 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_A1;
+#define RK30_PIN1_PA2 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_A2;
+#define RK30_PIN1_PA3 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_A3;
+#define RK30_PIN1_PA4 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_A4;
+#define RK30_PIN1_PA5 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_A5;
+#define RK30_PIN1_PA6 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_A6;
+#define RK30_PIN1_PA7 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_A7;
+#define RK30_PIN1_PB0 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_B0;
+#define RK30_PIN1_PB1 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_B1;
+#define RK30_PIN1_PB2 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_B2;
+#define RK30_PIN1_PB3 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_B3;
+#define RK30_PIN1_PB4 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_B4;
+#define RK30_PIN1_PB5 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_B5;
+#define RK30_PIN1_PB6 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_B6;
+#define RK30_PIN1_PB7 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_B7;
+#define RK30_PIN1_PC0 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_C0;
+#define RK30_PIN1_PC1 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_C1;
+#define RK30_PIN1_PC2 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_C2;
+#define RK30_PIN1_PC3 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_C3;
+#define RK30_PIN1_PC4 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_C4;
+#define RK30_PIN1_PC5 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_C5;
+#define RK30_PIN1_PC6 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_C6;
+#define RK30_PIN1_PC7 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_C7;
+#define RK30_PIN1_PD0 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_D0;
+#define RK30_PIN1_PD1 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_D1;
+#define RK30_PIN1_PD2 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_D2;
+#define RK30_PIN1_PD3 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_D3;
+#define RK30_PIN1_PD4 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_D4;
+#define RK30_PIN1_PD5 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_D5;
+#define RK30_PIN1_PD6 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_D6;
+#define RK30_PIN1_PD7 = (1 * RK_GPIO_BANK_OFFSET) + GPIO_D7;
+    //GPIO2
+#define RK30_PIN2_PA0 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_A0;
+#define RK30_PIN2_PA1 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_A1;
+#define RK30_PIN2_PA2 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_A2;
+#define RK30_PIN2_PA3 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_A3;
+#define RK30_PIN2_PA4 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_A4;
+#define RK30_PIN2_PA5 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_A5;
+#define RK30_PIN2_PA6 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_A6;
+#define RK30_PIN2_PA7 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_A7;
+#define RK30_PIN2_PB0 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_B0;
+#define RK30_PIN2_PB1 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_B1;
+#define RK30_PIN2_PB2 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_B2;
+#define RK30_PIN2_PB3 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_B3;
+#define RK30_PIN2_PB4 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_B4;
+#define RK30_PIN2_PB5 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_B5;
+#define RK30_PIN2_PB6 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_B6;
+#define RK30_PIN2_PB7 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_B7;
+#define RK30_PIN2_PC0 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_C0;
+#define RK30_PIN2_PC1 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_C1;
+#define RK30_PIN2_PC2 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_C2;
+#define RK30_PIN2_PC3 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_C3;
+#define RK30_PIN2_PC4 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_C4;
+#define RK30_PIN2_PC5 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_C5;
+#define RK30_PIN2_PC6 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_C6;
+#define RK30_PIN2_PC7 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_C7;
+#define RK30_PIN2_PD0 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_D0;
+#define RK30_PIN2_PD1 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_D1;
+#define RK30_PIN2_PD2 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_D2;
+#define RK30_PIN2_PD3 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_D3;
+#define RK30_PIN2_PD4 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_D4;
+#define RK30_PIN2_PD5 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_D5;
+#define RK30_PIN2_PD6 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_D6;
+#define RK30_PIN2_PD7 = (2 * RK_GPIO_BANK_OFFSET) + GPIO_D7;
+    //GPIO3
+#define RK30_PIN3_PA0 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_A0;
+#define RK30_PIN3_PA1 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_A1;
+#define RK30_PIN3_PA2 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_A2;
+#define RK30_PIN3_PA3 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_A3;
+#define RK30_PIN3_PA4 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_A4;
+#define RK30_PIN3_PA5 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_A5;
+#define RK30_PIN3_PA6 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_A6;
+#define RK30_PIN3_PA7 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_A7;
+#define RK30_PIN3_PB0 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_B0;
+#define RK30_PIN3_PB1 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_B1;
+#define RK30_PIN3_PB2 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_B2;
+#define RK30_PIN3_PB3 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_B3;
+#define RK30_PIN3_PB4 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_B4;
+#define RK30_PIN3_PB5 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_B5;
+#define RK30_PIN3_PB6 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_B6;
+#define RK30_PIN3_PB7 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_B7;
+#define RK30_PIN3_PC0 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_C0;
+#define RK30_PIN3_PC1 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_C1;
+#define RK30_PIN3_PC2 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_C2;
+#define RK30_PIN3_PC3 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_C3;
+#define RK30_PIN3_PC4 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_C4;
+#define RK30_PIN3_PC5 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_C5;
+#define RK30_PIN3_PC6 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_C6;
+#define RK30_PIN3_PC7 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_C7;
+#define RK30_PIN3_PD0 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_D0;
+#define RK30_PIN3_PD1 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_D1;
+#define RK30_PIN3_PD2 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_D2;
+#define RK30_PIN3_PD3 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_D3;
+#define RK30_PIN3_PD4 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_D4;
+#define RK30_PIN3_PD5 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_D5;
+#define RK30_PIN3_PD6 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_D6;
+#define RK30_PIN3_PD7 = (3 * RK_GPIO_BANK_OFFSET) + GPIO_D7;
+    //GPIO4
+#define RK30_PIN4_PA0 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_A0;
+#define RK30_PIN4_PA1 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_A1;
+#define RK30_PIN4_PA2 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_A2;
+#define RK30_PIN4_PA3 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_A3;
+#define RK30_PIN4_PA4 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_A4;
+#define RK30_PIN4_PA5 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_A5;
+#define RK30_PIN4_PA6 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_A6;
+#define RK30_PIN4_PA7 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_A7;
+#define RK30_PIN4_PB0 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_B0;
+#define RK30_PIN4_PB1 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_B1;
+#define RK30_PIN4_PB2 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_B2;
+#define RK30_PIN4_PB3 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_B3;
+#define RK30_PIN4_PB4 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_B4;
+#define RK30_PIN4_PB5 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_B5;
+#define RK30_PIN4_PB6 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_B6;
+#define RK30_PIN4_PB7 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_B7;
+#define RK30_PIN4_PC0 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_C0;
+#define RK30_PIN4_PC1 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_C1;
+#define RK30_PIN4_PC2 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_C2;
+#define RK30_PIN4_PC3 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_C3;
+#define RK30_PIN4_PC4 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_C4;
+#define RK30_PIN4_PC5 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_C5;
+#define RK30_PIN4_PC6 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_C6;
+#define RK30_PIN4_PC7 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_C7;
+#define RK30_PIN4_PD0 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_D0;
+#define RK30_PIN4_PD1 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_D1;
+#define RK30_PIN4_PD2 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_D2;
+#define RK30_PIN4_PD3 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_D3;
+#define RK30_PIN4_PD4 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_D4;
+#define RK30_PIN4_PD5 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_D5;
+#define RK30_PIN4_PD6 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_D6;
+#define RK30_PIN4_PD7 = (4 * RK_GPIO_BANK_OFFSET) + GPIO_D7;
+    //GPIO5
+#define RK30_PIN5_PA0 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_A0;
+#define RK30_PIN5_PA1 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_A1;
+#define RK30_PIN5_PA2 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_A2;
+#define RK30_PIN5_PA3 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_A3;
+#define RK30_PIN5_PA4 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_A4;
+#define RK30_PIN5_PA5 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_A5;
+#define RK30_PIN5_PA6 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_A6;
+#define RK30_PIN5_PA7 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_A7;
+#define RK30_PIN5_PB0 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_B0;
+#define RK30_PIN5_PB1 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_B1;
+#define RK30_PIN5_PB2 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_B2;
+#define RK30_PIN5_PB3 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_B3;
+#define RK30_PIN5_PB4 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_B4;
+#define RK30_PIN5_PB5 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_B5;
+#define RK30_PIN5_PB6 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_B6;
+#define RK30_PIN5_PB7 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_B7;
+#define RK30_PIN5_PC0 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_C0;
+#define RK30_PIN5_PC1 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_C1;
+#define RK30_PIN5_PC2 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_C2;
+#define RK30_PIN5_PC3 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_C3;
+#define RK30_PIN5_PC4 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_C4;
+#define RK30_PIN5_PC5 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_C5;
+#define RK30_PIN5_PC6 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_C6;
+#define RK30_PIN5_PC7 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_C7;
+#define RK30_PIN5_PD0 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_D0;
+#define RK30_PIN5_PD1 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_D1;
+#define RK30_PIN5_PD2 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_D2;
+#define RK30_PIN5_PD3 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_D3;
+#define RK30_PIN5_PD4 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_D4;
+#define RK30_PIN5_PD5 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_D5;
+#define RK30_PIN5_PD6 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_D6;
+#define RK30_PIN5_PD7 = (5 * RK_GPIO_BANK_OFFSET) + GPIO_D7;
+    //GPIO6
+#define RK30_PIN6_PA0 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_A0;
+#define RK30_PIN6_PA1 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_A1;
+#define RK30_PIN6_PA2 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_A2;
+#define RK30_PIN6_PA3 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_A3;
+#define RK30_PIN6_PA4 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_A4;
+#define RK30_PIN6_PA5 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_A5;
+#define RK30_PIN6_PA6 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_A6;
+#define RK30_PIN6_PA7 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_A7;
+#define RK30_PIN6_PB0 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_B0;
+#define RK30_PIN6_PB1 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_B1;
+#define RK30_PIN6_PB2 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_B2;
+#define RK30_PIN6_PB3 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_B3;
+#define RK30_PIN6_PB4 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_B4;
+#define RK30_PIN6_PB5 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_B5;
+#define RK30_PIN6_PB6 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_B6;
+#define RK30_PIN6_PB7 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_B7;
+#define RK30_PIN6_PC0 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_C0;
+#define RK30_PIN6_PC1 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_C1;
+#define RK30_PIN6_PC2 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_C2;
+#define RK30_PIN6_PC3 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_C3;
+#define RK30_PIN6_PC4 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_C4;
+#define RK30_PIN6_PC5 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_C5;
+#define RK30_PIN6_PC6 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_C6;
+#define RK30_PIN6_PC7 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_C7;
+#define RK30_PIN6_PD0 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_D0;
+#define RK30_PIN6_PD1 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_D1;
+#define RK30_PIN6_PD2 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_D2;
+#define RK30_PIN6_PD3 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_D3;
+#define RK30_PIN6_PD4 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_D4;
+#define RK30_PIN6_PD5 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_D5;
+#define RK30_PIN6_PD6 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_D6;
+#define RK30_PIN6_PD7 = (6 * RK_GPIO_BANK_OFFSET) + GPIO_D7;
+    //GPIO7
+#define RK30_PIN7_PA0 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_A0;
+#define RK30_PIN7_PA1 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_A1;
+#define RK30_PIN7_PA2 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_A2;
+#define RK30_PIN7_PA3 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_A3;
+#define RK30_PIN7_PA4 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_A4;
+#define RK30_PIN7_PA5 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_A5;
+#define RK30_PIN7_PA6 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_A6;
+#define RK30_PIN7_PA7 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_A7;
+#define RK30_PIN7_PB0 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_B0;
+#define RK30_PIN7_PB1 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_B1;
+#define RK30_PIN7_PB2 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_B2;
+#define RK30_PIN7_PB3 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_B3;
+#define RK30_PIN7_PB4 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_B4;
+#define RK30_PIN7_PB5 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_B5;
+#define RK30_PIN7_PB6 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_B6;
+#define RK30_PIN7_PB7 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_B7;
+#define RK30_PIN7_PC0 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_C0;
+#define RK30_PIN7_PC1 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_C1;
+#define RK30_PIN7_PC2 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_C2;
+#define RK30_PIN7_PC3 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_C3;
+#define RK30_PIN7_PC4 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_C4;
+#define RK30_PIN7_PC5 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_C5;
+#define RK30_PIN7_PC6 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_C6;
+#define RK30_PIN7_PC7 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_C7;
+#define RK30_PIN7_PD0 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_D0;
+#define RK30_PIN7_PD1 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_D1;
+#define RK30_PIN7_PD2 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_D2;
+#define RK30_PIN7_PD3 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_D3;
+#define RK30_PIN7_PD4 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_D4;
+#define RK30_PIN7_PD5 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_D5;
+#define RK30_PIN7_PD6 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_D6;
+#define RK30_PIN7_PD7 = (7 * RK_GPIO_BANK_OFFSET) + GPIO_D7;
+    //GPIO8
+#define RK30_PIN8_PA0 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_A0;
+#define RK30_PIN8_PA1 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_A1;
+#define RK30_PIN8_PA2 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_A2;
+#define RK30_PIN8_PA3 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_A3;
+#define RK30_PIN8_PA4 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_A4;
+#define RK30_PIN8_PA5 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_A5;
+#define RK30_PIN8_PA6 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_A6;
+#define RK30_PIN8_PA7 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_A7;
+#define RK30_PIN8_PB0 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_B0;
+#define RK30_PIN8_PB1 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_B1;
+#define RK30_PIN8_PB2 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_B2;
+#define RK30_PIN8_PB3 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_B3;
+#define RK30_PIN8_PB4 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_B4;
+#define RK30_PIN8_PB5 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_B5;
+#define RK30_PIN8_PB6 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_B6;
+#define RK30_PIN8_PB7 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_B7;
+#define RK30_PIN8_PC0 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_C0;
+#define RK30_PIN8_PC1 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_C1;
+#define RK30_PIN8_PC2 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_C2;
+#define RK30_PIN8_PC3 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_C3;
+#define RK30_PIN8_PC4 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_C4;
+#define RK30_PIN8_PC5 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_C5;
+#define RK30_PIN8_PC6 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_C6;
+#define RK30_PIN8_PC7 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_C7;
+#define RK30_PIN8_PD0 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_D0;
+#define RK30_PIN8_PD1 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_D1;
+#define RK30_PIN8_PD2 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_D2;
+#define RK30_PIN8_PD3 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_D3;
+#define RK30_PIN8_PD4 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_D4;
+#define RK30_PIN8_PD5 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_D5;
+#define RK30_PIN8_PD6 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_D6;
+#define RK30_PIN8_PD7 = (8 * RK_GPIO_BANK_OFFSET) + GPIO_D7;
+
diff --git a/external/iotest/setgpio.c b/external/iotest/setgpio.c
new file mode 100755
index 0000000..42f3c5f
--- /dev/null
+++ b/external/iotest/setgpio.c
@@ -0,0 +1,117 @@
+#include "rv11xx.h"
+
+
+int openGpioDev() 
+{
+    int ret=0;
+
+    fd = open("/dev/rockemd", O_RDWR);
+    if (fd < 0) {
+        ret=-1;
+    }
+    return ret;
+}
+
+int closeGpioDev() 
+{
+
+    int ret=0;
+    ret = close(fd);
+    if (fd < 0) {
+        ret=-1;
+    }
+    return ret;
+}
+
+int setGpioState(int num, int state) 
+{
+    int err=-1;
+    struct UserData userdata;
+    memset(&userdata,0x00, sizeof(userdata));
+    userdata.gpio=num;
+    userdata.state=state;
+
+    err = ioctl(fd, CMD_SET_GPIO, &userdata);
+    if(err<0){
+        err=-1;
+    }
+    return err;
+}
+
+int getGpioState(int num)
+{
+    int ret=-1;
+    struct UserData userdata;
+    memset(&userdata,0x00, sizeof(userdata));
+    userdata.gpio=num;
+
+    ret = ioctl(fd, CMD_GET_GPIO, &userdata);
+
+    return ret;
+}
+
+int releaseGpio(int num)
+{
+    int ret=-1;
+    struct UserData userdata;
+    memset(&userdata,0x00, sizeof(userdata));
+    userdata.gpio=num;
+    userdata.state=0;
+    ret = ioctl(fd, CMD_RELEASE_GPIO, &userdata);
+    return ret;
+}
+
+
+void main(int argc,char * argv[])
+{	
+	if(argc != 3) {
+		/*C =3 B =2 C5 = (3 -1 )*8+5 = 21*/
+		printf("************************************\n");
+		printf("    	GPIO_A0	=	 0				\n");
+		printf("    	GPIO_A1	=	 1				\n");
+		printf("    	GPIO_A2	=	 2				\n");
+		printf("    	GPIO_A3	=	 3				\n");
+		printf("    	GPIO_A4	=	 4				\n");
+		printf("    	GPIO_A5	=	 5				\n");
+		printf("    	GPIO_A6	=	 6				\n");
+		printf("    	GPIO_A7	=	 7				\n");
+		printf("    	GPIO_B0	=	 8				\n");
+		printf("    	GPIO_B1	=	 9				\n");
+		printf("    	GPIO_B2	=	 10				\n");
+		printf("    	GPIO_B3	=	 11				\n");
+		printf("    	GPIO_B4	=	 12				\n");
+		printf("    	GPIO_B5	=	 13				\n");
+		printf("    	GPIO_B6	=	 14				\n");
+		printf("    	GPIO_B7	=	 15				\n");
+		printf("    	GPIO_C0	=	 16				\n");
+		printf("    	GPIO_C1	=	 17				\n");
+		printf("    	GPIO_C2	=	 18				\n");
+		printf("    	GPIO_C3	=	 19				\n");
+		printf("    	GPIO_C4	=	 20				\n");
+		printf("    	GPIO_C5	=	 21				\n");
+		printf("    	GPIO_C6	=	 22				\n");
+		printf("    	GPIO_C7	=	 23				\n");
+		printf("    	GPIO_D0	=	 24				\n");
+		printf("    	GPIO_D1	=	 25				\n");
+		printf("    	GPIO_D2	=	 26				\n");
+		printf("    	GPIO_D3	=	 27				\n");
+		printf("    	GPIO_D4	=	 28				\n");
+		printf("    	GPIO_D5	=	 29				\n");
+		printf("    	GPIO_D6	=	 30				\n");
+		printf("    	GPIO_D7	=	 31				\n");
+		printf("(GPIO3_B0_d-->GPIO_LED0_OUT)=3*32+8=104 	\n");
+        printf("(GPIO3_B1_d-->GPIO_LED1_OUT)=3*32+9=105		\n");
+        printf("(GPIO3_B2_d-->GPIO_LED2_OUT)=3*32+10=106 	\n");
+		printf("(GPIO3_B3_d-->GPIO_SWITCH0)=3*32+11=107 	\n");
+		printf("(GPIO3_B4_d-->GPIO_SWITCH1)=3*32+12=108 	\n");
+        printf("please input gpio number + state 	\n");
+        printf("        setgpio 104 0				\n");
+        printf("************************************\n");
+        return -1;
+    }
+	int a = atoi(argv[1]);
+	int b = atoi(argv[2]);
+	openGpioDev();
+	setGpioState(a, b);
+	closeGpioDev();
+}
diff --git a/kernel/arch/arm/boot/dts/rv1126-evb-v10.dtsi b/kernel/arch/arm/boot/dts/rv1126-evb-v10.dtsi
new file mode 100755
index 0000000..321cddd
--- a/kernel/arch/arm/boot/dts/rv1126-evb-v10.dtsi
+++ b/kernel/arch/arm/boot/dts/rv1126-evb-v10.dtsi
+
+	rockemd_gpio {
+		compatible = "rockemd,gpio";
+	};
+
	cam_ircut0: cam_ircut {
		status = "okay";
		compatible = "rockchip,ircut";
		ircut-open-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;	//GPIO2_D1	IRCUT_ON
		ircut-close-gpios  = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;	//GPIO2_D2	IRCUT_OFF
		rockchip,camera-module-index = <1>;
		rockchip,camera-module-facing = "front";
	};

	dummy_codec: dummy-codec {
		compatible = "rockchip,dummy-codec";
		#sound-dai-cells = <0>;
	};
diff --git a/kernel/arch/arm/configs/rv1126_defconfig  b/kernel/arch/arm/configs/rv1126_defconfig 
new file mode 100755
index 0000000..2ef4e49
--- a/kernel/arch/arm/configs/rv1126_defconfig 
+++ b/kernel/arch/arm/configs/rv1126_defconfig 
CONFIG_SPI=y
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_SPIDEV=y
CONFIG_PINCTRL_RK805=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_ROCKEMD=y
CONFIG_POWER_AVS=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_POWER_RESET=y
diff --git a/kernel/drivers/gpio/Kconfig b/kernel/drivers/gpio/Kconfig
old mode 100644
new mode 100755
index 20466ee..8d7448f
--- a/kernel/drivers/gpio/Kconfig
+++ b/kernel/drivers/gpio/Kconfig
@@ -1388,4 +1388,8 @@ config GPIO_VIPERBOARD
 
 endmenu
 
+config GPIO_ROCKEMD
+	tristate "ROCKEMD GPIO RV1126&RV1109"
+	help
+	  ROCKEMD GPIO RV1126&RV1109.
 endif
diff --git a/kernel/drivers/gpio/Makefile b/kernel/drivers/gpio/Makefile
old mode 100644
new mode 100755
index c256aff..cec7d91
--- a/kernel/drivers/gpio/Makefile
+++ b/kernel/drivers/gpio/Makefile
@@ -159,3 +159,4 @@ obj-$(CONFIG_GPIO_ZEVIO)	+= gpio-zevio.o
 obj-$(CONFIG_GPIO_ZYNQ)		+= gpio-zynq.o
 obj-$(CONFIG_GPIO_ZX)		+= gpio-zx.o
 obj-$(CONFIG_GPIO_LOONGSON1)	+= gpio-loongson1.o
+obj-$(CONFIG_GPIO_ROCKEMD)	+= rockemd_gpio.o
\ No newline at end of file
diff --git a/kernel/drivers/gpio/rockemd_gpio.c b/kernel/drivers/gpio/rockemd_gpio.c
new file mode 100755
index 0000000..f410da8
--- /dev/null
+++ b/kernel/drivers/gpio/rockemd_gpio.c
@@ -0,0 +1,127 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+#include <linux/err.h>
+#include <linux/pwm.h>
+#include <linux/pwm_backlight.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/miscdevice.h>
+#include <linux/uaccess.h>
+
+struct UserData{
+		int gpio;
+		int state;
+};
+
+static struct of_device_id rockemd_of_match[] = {
+	{ .compatible = "rockemd,gpio" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rockemd_of_match);
+
+static int rockemd_open(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+static long rockemd_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	long ret = 0;
+	struct UserData userdata;
+
+	switch (cmd){
+		case 0:
+			if (copy_from_user((void*)&userdata,(void __user *)arg, sizeof(struct UserData)))
+				return -EFAULT;
+			if (gpio_is_valid(userdata.gpio)) {
+				ret=gpio_direction_input(userdata.gpio);
+				if (ret) {
+					printk("failed to gpio_direction_input  for you ret:%d\n",userdata.gpio);
+				}
+				userdata.state = gpio_get_value(userdata.gpio);
+				return userdata.state;
+			} else
+				return -EFAULT;
+			break;
+		case 1:
+			if (copy_from_user((void*)&userdata,(void __user *)arg, sizeof(struct UserData)))
+				return -EFAULT;
+			if (gpio_is_valid(userdata.gpio)) {
+				ret=gpio_direction_output(userdata.gpio, userdata.state);
+				if (ret) {
+					printk("failed to gpio_direction_output  for you ret:%d\n",userdata.gpio);
+				}
+			} else
+				return -EFAULT;
+			break;
+		case 2:
+			if (copy_from_user((void*)&userdata,(void __user *)arg, sizeof(struct UserData)))
+				return -EFAULT;
+			printk("copy_from_user  gpio=%d ,state=%d\n",userdata.gpio,userdata.state);
+			gpio_free(userdata.gpio);
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+	}
+	return ret;
+}
+
+static int rockemd_release(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+static struct file_operations rockemd_fops = {
+	.owner   = THIS_MODULE,
+	.open    = rockemd_open,
+	.unlocked_ioctl   = rockemd_ioctl,
+	.release = rockemd_release,
+};
+
+static struct miscdevice rockemd_dev = {
+    .minor = MISC_DYNAMIC_MINOR,
+    .name = "rockemd",
+    .fops = &rockemd_fops,
+};
+
+static int rockemd_probe(struct platform_device *pdev)
+{
+    int ret=-1;
+	ret = misc_register(&rockemd_dev);
+	if (ret < 0){
+		printk("misc_register err!\n");
+		return ret;
+	}
+    printk("func: %s\n", __func__);
+    return 0;
+}
+
+static int rockemd_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver rockemd_driver = {
+	.driver		= {
+		.name		= "rockemd",
+		.owner		= THIS_MODULE,
+		.of_match_table	= of_match_ptr(rockemd_of_match),
+	},
+	.probe		= rockemd_probe,
+	.remove		= rockemd_remove,
+};
+
+module_platform_driver(rockemd_driver);
+MODULE_AUTHOR("rockemd <rockemd2020@163.com>");
+MODULE_DESCRIPTION("rockemd Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:rockemd");
\ No newline at end of file

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