SystemVerilog：Chapter 3，Net and Variable types

本文链接：https://blog.csdn.net/penglei_123456789/article/details/123207296

本文详细介绍了SystemVerilog中的变量类型，包括可综合的logic和bit型，以及不再推荐使用的reg型。强调在RTL模型中使用4-state的logic类型，避免2-state类型以防止错误。此外，讨论了变量声明规则，如标量和矢量变量的声明，并提到了变量赋值的限制。最后，指出了变量赋值只能由单一源进行。

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3.4 Variable types

Variables provide temporary storage for simulation.

The temporary storage required by simulation does not necessarily mean that actual silicon will require storage.

always_comb  begin
    sum = a + b; 
end

The always_comb procedure in the preceding code snippet will be implemented as combinational logic in silicon. sum not require any type of storage in hardware.

always_ff @(posedge elk)  begin
    if (!rstN) 
        out <= '0; 
    else 
        out <= sum;
end

On the other hand, the always_ff procedure will be implemented in silicon as a flip-flop, which is a hardware storage device.

3.4.1 Synthesizable variable data types

Variables are declared by specifying both a type and a data type. The type is the keyword var, which can be specified explicitly or implicitly inferred.

The var keyword is seldom used in actual SystemVerilog code.

SystemVerilog has keywords for several built-in variable data types. These keywords infer a either var logic (4-state) or var bit (2-state) variable type.

可综合的系统变量数据类型就两种 logic型和 bit型，其他的如 reg、integer、int等都是在这两种基础上面的延申，具体见下表：

Note：Use the 4-state logic data type to infer variables in RTL models. Do not use 2-state types in RTL models. An exception to this guideline is to use the int type to declare for-loop iterator variables.（for 循环中使用int型，其他RTL models 中使用 4-state logic data type）。

1.The context dependent logic data type.

当作为 4-state 变量类型时，logic 相当于 reg。但 logic并不仅仅表示变量类型，同时logic还表示 a net type with 4-state values。

A net type will be inferred, when logic is used in conjunction with the declaration of a module input or inout port 。

A variable is inferred when the logic keyword is used by itself, or in conjunction with the declaration of a module output port.

2.The obsolete reg data type.

The reg data type is an obsolete data type left over from the original Verilog language. The logic type should be used instead of reg.

Using logic instead of reg can help prevent this misconception that a hardware register will be inferred.

3.Avoid 2-state data types in RTL models.

Since 2- state data types can only have a 0 or 1 value, a design with errors can appear to be functioning correctly during simulation. This is not good!

An appropriate place to use 2-state variables is for randomized stimulus in verification testbenches.

4.Non synthesizable variable types.

SystemVerilog has several variable types that are intended primarily for verification, and are not generally supported by RTL synthesis compilers.