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RSS订阅原创 UVM Virtual Sequence
uvm_declare_p_sequencer(virtual_jelly_bean_sequencer)//使用p_sequencer//实例化两个sequence//将如下的两个真实的seq连接到seqr并顺序执行forkjoinendtaskendclass//直接在vir_seq中创建两个真实的sequencer 句柄//实例化两个sequence//将如下的两个真实的seq连接到seqr并顺序执行forkjoin。
2023-06-21 19:39:19
201
原创 SV,class学习笔记五、参数化类(parameterized class)
systemveriolg parameteriaed class
2022-09-18 15:16:42
1551
原创 SV，class学习笔记三，虚方法(virtual method)、多态(polymorphic)
virtual SystemVerilog class cast
2022-09-16 12:21:47
490
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原创 SystemVerilog class章节 （2）静态变量、typedef
systemVerilog 、static 、class、 typedef
2022-09-15 16:56:55
294
原创 System Verilog Arrays （数组）
2. unpacked arrays unpacked arrays 的变量可以是任何的数据类型 logic、bit、byte等，变量的大小可以是一个范围[0:size-1] 也可以是一个数字[size]。`timescale 1ns/1ps// test modulemodule tb; logic data [2] [4]; initial begin foreach(data[i]) foreach(data[i][j]) begin ...
2022-03-10 22:03:23
195
原创 System Verilog Arrays （数组）
1. Packed Arrays在SV中有两种数组类型，一类是packed arrays，另一类是unpacked arrays。packed arrays 的维度定义在变量名之前，unpacked arrays 的维度定义在变量名之后。一维的packed arrays 也叫做vector。bit [7:0] c1; // packed arrays 或者 vector logic [3:0] [7:0] c2 ...
2022-03-10 21:40:42
363
原创 SystemVerilog：Chapter 3，Net and Variable types_4
3.4 Variable typesVariables provide temporary storage for simulation.The temporary storage required by simulation does not necessarily mean that actual silicon will require storage.always_comb begin sum = a + b; endTh...
2022-03-01 17:17:20
347
原创 SystemVerilog：Chapter 3，Net and Variable types_3
3.3 Types and data typesSystemVerilog provides two general groups of data types, nets and variables.Data types are used by software tools, such as simulators and synthesis compilers, to determine how to store data and process changes ...
2022-03-01 15:03:52
46
原创 SystemVerilog：Chapter 3，Net and Variable types_2
3.2 Literal values (numbers)3.2.2 Vector fill literal valuesSystem Verilog provides a special form of unsized literal integers that sets all bits of a vector of any size to 0, 1, X or Z.An example of using the vector fill literal integers is:...
2022-03-01 14:23:37
53
原创 SystemVerilog：Chapter 3，Net and Variable types_1
3.1 Literal values (numbers)3.2.1 Literal integer values1.Simple decimal literal integersA literal integer value can be specified as a simple number, such as the number 9。result = d + 9 ；A simple literal number is treated by simulation an...
2022-03-01 14:10:40
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