ColdFire and 68K

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Instruction Set

 

Although the ColdFire architecture is closely related to the 680x0, there are many simplifications to the instruction set. Nearly all of the differences are omissions from the 680x0 instruction set and addressing modes. This means that (with a few important exceptions detailed below), a 680x0 instruction which is implemented in ColdFire behaves in exactly the same way under the two architectures. In fact, almost all user-level (and much supervisor-level) ColdFire code can be run unchanged on a 68020 or later 680x0 processor (apart from new instructions introduced in the Version 4 ColdFire core). The converse, however, is not the case.

 

Principles behind the differences

 

In order to understand the ColdFire instruction set in relation to that of the 680x0, it helps to have an appreciation of why the simplifications have been made. The philosophy behind ColdFire is influenced by the success of RISC processors in providing high performance - for a given degree of chip complexity - by eliminating seldom-used instructions and complex addressing modes, and by regularizing the instruction set to make it easier for the hardware to optimize despatch of the instruction stream.

 

However, standard RISC processors such as the PowerPC achieve high performance at the expense of low code density, in part because all instructions are the same width (generally 4 bytes) and also because only very simple addressing modes are available. In addition, RISC processors do not allow direct modification of memory locations; all memory reads and writes have to go via registers. This all means that programs compiled for RISC processors tend to be substantially larger than those compiled for CISC architectures such as the 680x0. This penalty does not greatly matter for desktop systems or servers with 32MB or more of RAM, but for embedded applications it can be a significant disadvantage, both in terms of system cost and power consumption.

 

The ColdFire architecture - which Freescale Semiconductor characterizes as "Variable-Length RISC" - aims to share many of the speed advantages of RISC, without losing too much of the code density advantages of the 680x0 family. Like most modern processor architectures, it is optimized for code written in C or C++, and instructions which are not frequently generated by compilers are amongst those removed from the instruction set. Some of the complex addressing modes - again not important for compilers - are eliminated, and the additional hardware complexities involved in supporting arithmetic operations on bytes and words also disappear. In order to regularize the instruction stream, all ColdFire instructions are either 2, 4 or 6 bytes wide; this is why certain combinations of source and destination operands are not available.

 

Missing addressing modes

The ColdFire addressing modes are quite similar to those of the original 68000, i.e. without the extensions introduced in the 68020 and later processors, but with some differences in indexed addressing.

 

Missing instructions

A number of instructions are not implemented at all under ColdFire.

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The Coldfire has almost the same programming model as the 68k. There are a few extra instructions (especially for cores with extra functionality, like a MAC unit), and it is missing some of the more obtuse addressing modes from
later 68k chips. Otherwise, the real difference between the cores is that the Coldfire is far more efficient. There are, of course, huge differences between individual Coldfire chips and a 68000 chip - the ColdFire series are
microcontrollers with lots of built-in peripherals, rather than just a plain cpu.

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The ColdFire® family combines both benefits of CISCs and RISCs worlds by keeping the same architecture that most customers are familiar and comfortable with, but offering a much higher performance than CISC. ColdFire® processors are based on the concept of a variable-length reduced instruction set (RISC) architecture.

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