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ISE
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ERROR: [Synth 8-439] module ‘design_system_new_v_mix_0_0‘ not found 错误解决办法【2022是个越不过去的砍】
ERROR: [Synth 8-439] module 'design_system_new_v_mix_0_0' not found 错误解决办法【2022是个越不过去的砍】原创 2022-05-30 16:34:06 · 3545 阅读 · 0 评论 -
Vivado新年2022大彩蛋Bug|ERROR:[IMPL 213-28] Failed to generate IP 和 [Vivado 12-5601] Launch HLS failed
Vivado新年2022大彩蛋Bug|ERROR:[IMPL 213-28] Failed to generate IP 和 [Vivado 12-5601] Launch HLS failed原创 2022-01-12 16:10:47 · 3918 阅读 · 6 评论 -
2020-11-14 Solved “-Detected python version is less than the expected 2.7.3“
I have installed a new version "Ubuntu 20.1" , and try to install "Petalinux 2018.3",however, I meet a problem that the installation is aborted with the follow error message:ERROR: You have tools that don't meet the version requirements:-Detected py.原创 2020-11-14 16:24:53 · 2118 阅读 · 2 评论 -
Vivado 下 [Labtoolstcl 44-494] There is no active target available for server at localhost.Targets(s)
Vivado2019.1下连不上Cable USB仿真器。弹窗显示错误[Labtoolstcl 44-494] There is no active target available for server at localhost.Targets(s)产生原因:因为我想烧写ISE,把驱动通过指令方式切换了一下。再回到Vivado下就连不上仿真器了。D:cd Xilinx\14.6\ISE_DS\ISE\bin\nt64\wdreg -inf uninstall.inf -silent -l.原创 2020-10-07 16:20:26 · 5834 阅读 · 5 评论 -
Bridge from "Video In to AXI4-stream" to "AXI4-stream to Video Out" directly with VTC without VDMA
xilinx vivado下通常的视频流设计,都采用Vid In toaxi4stream --> VDMA write --> MM --> VDMA read --> axi4 stream to video out这样的路径。网上例子很多,官方参考也有xapp521,实现起来参考无压力。但这套方案明显的问题是,缓存图像带来帧延迟,对于一些延迟要求高的任务,反倒...原创 2020-03-07 00:12:46 · 2003 阅读 · 2 评论 -
DDR3 MIG生成的ucf直接复制使用在translate步骤约束部分报错问题解决办法
DDR3 MIG生成的ucf直接复制使用在translate步骤约束部分报错问题解决办法原创 2016-08-05 17:30:34 · 3443 阅读 · 1 评论 -
Xilinx ISE Map过程时间过长的解决
最近在Kintex 7上开发新的项目,骤然发现曾经在Virtex 5和Spartan 6上移植过来的成熟算法,综合布线时出现Map时间非常漫长的现象。这个漫长不是一般的长,打个比方,以前在Virtex 5下同一个算法完成全部综合布线仅用10分钟,在Kintex 7下却耗时长达7~8个小时。从console窗看,常常卡在7.8 或8.8 global placement这一步,后面有很多....原创 2015-04-28 22:37:36 · 11392 阅读 · 3 评论