STM32之MAX14830

最新推荐文章于 2021-10-10 11:21:59 发布

夕阳下的枫林

最新推荐文章于 2021-10-10 11:21:59 发布

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分类专栏： ARM 文章标签： MAX14830

本文链接：https://blog.csdn.net/pxy198831/article/details/102946970

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驱动如下：

/******************************************************************************
* 文 件  名 称:BspMax14830.c
* 文件功能概述:实现MAX14830驱动接口
* 文 件  作 者:   
* 版        本:V1.0.0.0
* 修 订  记 录:2018-4-28创建
******************************************************************************/
#include "BspMax14830.h"
/*
 * 数据类型-SPI端口信息
 */
typedef struct
{
  S_GpioCtrl sCsCtrl;
  S_GpioCtrl sRstCtrl;
  S_ExtiCtrl sIntCtrl;
}S_Max14830PortConf;

/*
 * 用于记录SPI的端口信息,包括SCK MISO MOSI
 */
static S_Max14830PortConf stMax14830Port[E_MAX14830_MAX] = 
{
  {
    {RCC_AHB1Periph_GPIOF, GPIOF, GPIO_Pin_6},
    {RCC_AHB1Periph_GPIOI, GPIOI, GPIO_Pin_10},
		{RCC_AHB1Periph_GPIOH, GPIOH, GPIO_Pin_7}
//    {RCC_AHB1Periph_GPIOI, GPIOI, GPIO_Pin_11,  EXTI_PortSourceGPIOI, EXTI_PinSource11,  0, EXTI15_10_IRQn, EXTI_Line11}
  }
};

/* Max14830扩展串口相关操作 */
const E_SPIx stMax14830Spi[E_MAX14830_MAX] = {E_SPI_4};
static uint8 stMax14830Led[E_MAX14830_MAX][4];


static __inline void Max14830_CS_ENABLE(E_MAX14830x eMax14830)
{
	GPIO_ResetBits(stMax14830Port[eMax14830].sCsCtrl.GPIOx, stMax14830Port[eMax14830].sCsCtrl.GPIOxPinx);
}

static __inline void Max14830_CS_DISABLE(E_MAX14830x eMax14830)
{
	GPIO_SetBits(stMax14830Port[eMax14830].sCsCtrl.GPIOx, stMax14830Port[eMax14830].sCsCtrl.GPIOxPinx);
}

static void Max14830_Reset(E_MAX14830x eMax14830)
{
  GPIO_SetBits(stMax14830Port[eMax14830].sRstCtrl.GPIOx, stMax14830Port[eMax14830].sRstCtrl.GPIOxPinx);
  GPIO_ResetBits(stMax14830Port[eMax14830].sRstCtrl.GPIOx, stMax14830Port[eMax14830].sRstCtrl.GPIOxPinx);
  DelayMs(20);
  GPIO_SetBits(stMax14830Port[eMax14830].sRstCtrl.GPIOx, stMax14830Port[eMax14830].sRstCtrl.GPIOxPinx);
	DelayMs(20);
}

static void Max14830_WriteRegister(E_MAX14830x eMax14830, uint8 u8_ch, uint8 u8_addr, uint8 u8_dat)
{

	
	uint8 u8_temp = 0;
	
	u8_temp = Max14830_WRITE | (u8_ch<<5) | (u8_addr&0x1F);
	
  Max14830_CS_ENABLE(eMax14830);
	SPIxWriteReadByte(stMax14830Spi[eMax14830], &u8_temp, NULL);
	SPIxWriteReadByte(stMax14830Spi[eMax14830], &u8_dat, NULL);
	Max14830_CS_DISABLE(eMax14830);
}

static uint8 Max14830_ReadRegister(E_MAX14830x eMax14830, uint8 u8_ch, uint8 u8_addr)
{

	
	uint8 u8_temp = 0;
	
	u8_temp = Max14830_READ | (u8_ch<<5) | (u8_addr&0x1F);
	
  Max14830_CS_ENABLE(eMax14830);
	SPIxWriteReadByte(stMax14830Spi[eMax14830], &u8_temp, NULL);
	SPIxWriteReadByte(stMax14830Spi[eMax14830], NULL, &u8_temp);
	Max14830_CS_DISABLE(eMax14830);
	
	return u8_temp;
}

uint32 u32_Max14830RefClk[E_MAX14830_MAX]={0};
__inline static uint8 IsCurMinError(uint32 u32_clk, uint32 *min_error)
{
  uint32 u32_err = u32_clk%(115200*16);
  
  if (*min_error > u32_err)
  {
		*min_error = u32_err;
		return 0;
	}
  else
  {
    return 1;  
  }
}
static sint8 Max14830_SelectRefClk(E_MAX14830x eMax14830, uint8 u8_ch, uint32 u32_xtal_clk)
{
  uint32 u32_min_error = 0xFFFFFFFF;
  uint32 u32_clk=0,u32_pll_clk=0,u32_ref_clk=0;
  uint8 u8_pll_cfg_value = 0x00;
  uint8 u8_div = 1;
	uint8 i=0;
  
  if(0 == IsCurMinError(u32_xtal_clk,&u32_min_error))
  {
    u8_pll_cfg_value = 0x01;
    u32_ref_clk = u32_xtal_clk;
  }
  else
  {
    /* do noting */
  }

  for(u8_div=1;u8_div<64;u8_div++)
  {
    u32_clk = u32_xtal_clk/u8_div;
    /* Try multiplier 6 */
		u32_pll_clk = u32_clk * 6;
		if ((u32_clk >= 500000) && (u32_clk <= 800000))
    {
      if (0==IsCurMinError(u32_pll_clk, &u32_min_error)) 
      {
				u8_pll_cfg_value = (0 << 6) | u8_div;
				u32_ref_clk = u32_pll_clk;
			}
    }
			
		/* Try multiplier 48 */
		u32_pll_clk = u32_clk * 48;
		if ((u32_clk >= 850000) && (u32_clk <= 1200000))
    {
      if (0==IsCurMinError(u32_pll_clk, &u32_min_error)) 
      {
				u8_pll_cfg_value = (1 << 6) | u8_div;
				u32_ref_clk = u32_pll_clk;
			}
    }
			
		/* Try multiplier 96 */
		u32_pll_clk = u32_clk * 96;
		if ((u32_clk >= 425000) && (u32_clk <= 1000000))
    {
      if (0==IsCurMinError(u32_pll_clk, &u32_min_error)) 
      {
				u8_pll_cfg_value = (2 << 6) | u8_div;
				u32_ref_clk = u32_pll_clk;
			}
    }
			
		/* Try multiplier 144 */
		u32_pll_clk = u32_clk * 144;
		if ((u32_clk >= 390000) && (u32_clk <= 667000))
    {
      if (0==IsCurMinError(u32_pll_clk, &u32_min_error)) 
      {
				u8_pll_cfg_value = (3 << 6) | u8_div;
				u32_ref_clk = u32_pll_clk;
			}
    }
  }
  
  if(0!=u8_pll_cfg_value)
  {
		for(i=0;i<3;i++)
		{
			Max14830_WriteRegister(eMax14830, u8_ch, MAX310X_PLLCFG_REG, u8_pll_cfg_value);
		  Max14830_WriteRegister(eMax14830, u8_ch, MAX310X_CLKSRC_REG, MAX310X_CLKSRC_PLL_BIT);
			if(
				(Max14830_ReadRegister(eMax14830, u8_ch, MAX310X_PLLCFG_REG)==u8_pll_cfg_value) && 
		    (Max14830_ReadRegister(eMax14830, u8_ch, MAX310X_CLKSRC_REG)==MAX310X_CLKSRC_PLL_BIT)
		  	)
			{
				break;
			}
		}
		
		if(i>3)
		{
			return -1;
		}
  }
  else
  {
    return -1;
  }
  
  u32_Max14830RefClk[eMax14830] = u32_ref_clk;
	return 0;
}


/*u16_len参数不要大于128*/
sint32 Max14830xWriteBytes(E_MAX14830x eMax14830,uint8 u8_sub_ch, uint8_t *p_data, uint16_t u16_len)
{
	uint8 u8_temp = 0;
	uint16 i = 0,u16_idle_len = 0;
	uint8 u8RegDat = 0x00;

	u8RegDat = Max14830_ReadRegister(eMax14830,u8_sub_ch,MAX310X_MODE1_REG);
	Max14830_WriteRegister(eMax14830,u8_sub_ch,MAX310X_MODE1_REG,u8RegDat|0x02);  //填充14830发送区之前先关闭发送
	
	u16_idle_len = 128 - Max14830_ReadRegister(eMax14830,u8_sub_ch,MAX310X_TXFIFOLVL_REG); //获取14830发送区可用大小
	if(u16_len > u16_idle_len)
	{
		u16_len = u16_idle_len;
	}
	
	stMax14830Led[eMax14830][u8_sub_ch] = stMax14830Led[eMax14830][u8_sub_ch]^0x08;
	Max14830_WriteRegister(eMax14830,u8_sub_ch,MAX310X_GPIODATA_REG,stMax14830Led[eMax14830][u8_sub_ch]);
	
	u8_temp = Max14830_WRITE | (u8_sub_ch<<5) | (MAX310X_THR_REG&0x1F);
	
	Max14830_CS_ENABLE(eMax14830);
	
	SPIxWriteReadByte(stMax14830Spi[eMax14830], &u8_temp, NULL);
	for(i=0;i<u16_len;i++)
	{
		SPIxWriteReadByte(stMax14830Spi[eMax14830], p_data, NULL);
		p_data ++;
	}
	Max14830_CS_DISABLE(eMax14830);
	
	Max14830_WriteRegister(eMax14830,u8_sub_ch,MAX310X_MODE1_REG,u8RegDat&0xFD);//填充完成后启动发送
	
	return u16_len;
}

sint32 Max14830xReadBytes(E_MAX14830x eMax14830,uint8 u8_sub_ch, uint8_t *p_data, uint16_t u16_len)
{
	uint8 u8_temp1, u8_temp2= 0;
	uint16 i = 0;
	uint16 len_r = 0;
	
	u8_temp1 = Max14830_READ | (u8_sub_ch<<5) | (MAX310X_RHR_REG&0x1F);
	
  Max14830_CS_ENABLE(eMax14830);
	SPIxWriteReadByte(stMax14830Spi[eMax14830], &u8_temp1, NULL);
	for(i=0;i<u16_len;i++)
	{  
	  SPIxWriteReadByte(stMax14830Spi[eMax14830], NULL, &u8_temp2);
		*p_data++ = u8_temp2;
		len_r++;
	}

	Max14830_CS_DISABLE(eMax14830);
	
	return len_r;	
}

static uint8 Max14830_WaitReady(E_MAX14830x eMax14830)
{  
	uint8 u8_reg_dat = 0,i = 0;
	RCC_AHB1PeriphClockCmd(stMax14830Port[eMax14830].sIntCtrl.GPIOxSource, ENABLE);

	for(i=0;i<3;i++)
	{
		Max14830_Reset(eMax14830);
	
	  /* enter expand-register to read REVID */
    Max14830_WriteRegister( eMax14830,0,0x1F,MAX310X_EXTREG_ENBL);
	  u8_reg_dat = Max14830_ReadRegister( eMax14830,0,0x05);
    Max14830_WriteRegister( eMax14830,0,0x1F,MAX310X_EXTREG_DSBL);
		if((u8_reg_dat&0xB0) == 0xB0)
	  {
	  	break;
	  }
	}
	
	if(i > 3)
	{
		return 1;
	}
	else
	{
	  return 0;
	}
}

//static void Max14830_SetIrq(E_MAX14830x eMax14830)
//{
//	/* 中断引脚 */
//	EXTI_InitTypeDef   EXTI_InitStructure;
//	NVIC_InitTypeDef   NVIC_InitStructure;

//	RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);

//  SYSCFG_EXTILineConfig(stMax14830Port[eMax14830].sIntCtrl.EXTIxPortSource, stMax14830Port[eMax14830].sIntCtrl.EXTIxPinSource);
//  
//  EXTI_InitStructure.EXTI_Line = stMax14830Port[eMax14830].sIntCtrl.EXTIxLine;
//  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
//  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
//  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
//  EXTI_Init(&EXTI_InitStructure);
//    
//  NVIC_InitStructure.NVIC_IRQChannel = stMax14830Port[eMax14830].sIntCtrl.EXTIxIRQn;
//  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x04;
//  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x00;
//  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
//  NVIC_Init(&NVIC_InitStructure);
//}

static sint8 Max14830_InitPort(E_MAX14830x eMax14830)
{ 
	GPIO_InitTypeDef GPIO_InitStructure;
  if(eMax14830 < E_MAX14830_MAX)
  {
     /* CS 引脚 */
    RCC_AHB1PeriphClockCmd(stMax14830Port[eMax14830].sCsCtrl.GPIOxSource, ENABLE);
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    
    GPIO_InitStructure.GPIO_Pin = stMax14830Port[eMax14830].sCsCtrl.GPIOxPinx;
    GPIO_Init(stMax14830Port[eMax14830].sCsCtrl.GPIOx, &GPIO_InitStructure);
    
    GPIOxWriteBit(stMax14830Port[eMax14830].sCsCtrl.GPIOx,stMax14830Port[eMax14830].sCsCtrl.GPIOxPinx,1);
    
    return 0;
  }
  else
  {
    return -1;
  }
}


static sint8 Max14830_SetMode(E_MAX14830x eMax14830,uint8 u8_ch,uint8 u8_mode)
{
  uint8 u8Dat = 0;
	#define MODE1 0x09
	#define MODE2 0x0A
	#define LCR 0x0B
	
	Max14830_WriteRegister( eMax14830,u8_ch,MAX310X_MODE1_REG,MAX310X_MODE1_TRNSCVCTRL_BIT);  //disable auto_dirctrion ,disable rx
	u8Dat = MAX310X_MODE2_FIFORST_BIT;
  Max14830_WriteRegister( eMax14830,u8_ch,MAX310X_MODE2_REG,u8Dat);  
  if(u8_ch == 0x02)
  {
    u8Dat |= MAX310X_MODE2_MULTIDROP_BIT;
    Max14830_WriteRegister( eMax14830,u8_ch,MAX310X_MODE2_REG,u8Dat);
    
	  Max14830_WriteRegister( eMax14830,u8_ch,MAX310X_LCR_REG, 
                            MAX310X_LCR_PARITY_BIT
                           |MAX310X_LCR_EVENPARITY_BIT
                           |MAX310X_LCR_FORCEPARITY_BIT
                           |MAX310X_LCR_WORD_LEN_8);   
  }
  else
  {
    Max14830_WriteRegister( eMax14830,u8_ch,MAX310X_LCR_REG, MAX310X_LCR_WORD_LEN_8);   
  }
  u8Dat &=~ MAX310X_MODE2_FIFORST_BIT;
	Max14830_WriteRegister( eMax14830,u8_ch,MAX310X_MODE2_REG,u8Dat);  
	return 0;
}

static sint8 Max14830_SetBaud(E_MAX14830x eMax14830,uint8 u8_ch,uint32 u32_baud)
{
	float  TempDiv = 0.0f;
	uint8  BrgConfig = 0,DivMsb=0,DivLsb=0;
	
	if(u32_Max14830RefClk[eMax14830] != 0)
	{
	  TempDiv = (float)u32_Max14830RefClk[eMax14830]/(float)u32_baud/16.0F;
		DivLsb = ((uint32)TempDiv)&0xFF;
		DivMsb = (((uint32)TempDiv)>>8)&0xFF;
		TempDiv = TempDiv - ((uint32)TempDiv);
		BrgConfig = (uint8)(TempDiv*16);
		
		Max14830_WriteRegister(eMax14830,u8_ch,MAX310X_BRGCFG_REG,BrgConfig);
		Max14830_WriteRegister(eMax14830,u8_ch,MAX310X_BRGDIVLSB_REG,DivLsb);
		Max14830_WriteRegister(eMax14830,u8_ch,MAX310X_BRGDIVMSB_REG,DivMsb);
		
		return 0;
	}
	else
	{
		return -1;
	}
}

static sint8 Max14830_DisableClk(E_MAX14830x eMax14830,uint8 u8_ch)
{
	uint8 u8_data = 0xFF;
	u8_data = Max14830_ReadRegister(eMax14830,u8_ch,MAX310X_BRGCFG_REG);
	u8_data |= 0x40;
	Max14830_WriteRegister(eMax14830,u8_ch,MAX310X_BRGCFG_REG,u8_data);
	u8_data = Max14830_ReadRegister(eMax14830,u8_ch,MAX310X_BRGCFG_REG);
	if((u8_data&0x40) != 0x00)
	{
		return 0;
	}
	else
	{
		return -1;
	}
}

static sint8 Max14830_EnableClk(E_MAX14830x eMax14830,uint8 u8_ch)
{
	uint8 u8_data = 0xFF;
	u8_data = Max14830_ReadRegister(eMax14830,u8_ch,MAX310X_BRGCFG_REG);
	u8_data &= ~0x40;
	Max14830_WriteRegister(eMax14830,u8_ch,MAX310X_BRGCFG_REG,u8_data);
	if((u8_data&0x40) != 0x00)
	{
		return -1;
	}
	else
	{
		return 0;
	}
}

static sint8 Max14830_InitModule(E_MAX14830x eMax14830, uint8 u8_ch)
{ 
	uint8 i=0;
	sint8 s8_ret = 0;
		
	for(i=0;i<3;i++)
	{
    s8_ret = 0x00;				
	  s8_ret |= Max14830_DisableClk(eMax14830,u8_ch);
	  s8_ret |= Max14830_SetMode(eMax14830,u8_ch,0);
    s8_ret |= Max14830_SetBaud(eMax14830,u8_ch,9600);
		Max14830_WriteRegister(eMax14830,u8_ch,MAX310X_GPIOCFG_REG,0x08);
		Max14830_WriteRegister(eMax14830,u8_ch,MAX310X_GPIODATA_REG,0x00);
		stMax14830Led[eMax14830][u8_ch] =  Max14830_ReadRegister(eMax14830,u8_ch,MAX310X_GPIODATA_REG);
	  //Max14830_SetIrq(eMax14830);
	  s8_ret |= Max14830_EnableClk(eMax14830,u8_ch);
		if(s8_ret == 0x00)
		{
			break;
		}
	}
		
  if(i > 3)
  {
	  return -1;
	}
  else
  {
    return 0;
  }
}

sint8 Max14830_Init(E_MAX14830x eMax14830)
{
	uint8 u8_ch = 0;
	sint8 s8_ret = 0;
	
	if(eMax14830 < E_MAX14830_MAX)
  {
	  SPIxInit(stMax14830Spi[eMax14830]);	
    Max14830_InitPort(eMax14830);
		
	  if(
			(0 == Max14830_WaitReady(eMax14830))&&
		  (0 == Max14830_SelectRefClk(eMax14830,0,12000000))
		  )
	  {
		  for(u8_ch=0;u8_ch<4;u8_ch++)
		  {
		  	if(Max14830_InitModule(eMax14830,u8_ch) != 0x00)
		  	{
		  		s8_ret |= (1<<u8_ch);
		  	}
		  }
	  } 
		else
    {
	  	s8_ret = -1;
	  }
	}
	else
  {
		s8_ret = -1;
	}
	
	return s8_ret;
}

void Max14830_ResetModule(E_MAX14830x eMax14830, uint8 u8_ch)
{
	if((eMax14830<E_MAX14830_MAX) && (u8_ch<4))
  {
	  Max14830_DisableClk(eMax14830,u8_ch);
	  Max14830_SetMode(eMax14830,u8_ch,0);
    Max14830_SetBaud(eMax14830,u8_ch,9600);
	  Max14830_WriteRegister(eMax14830,u8_ch,MAX310X_GPIOCFG_REG,0x08);
	  Max14830_WriteRegister(eMax14830,u8_ch,MAX310X_GPIODATA_REG,0x00);
	  stMax14830Led[eMax14830][u8_ch] =  Max14830_ReadRegister(eMax14830,u8_ch,MAX310X_GPIODATA_REG);
	  //Max14830_SetIrq(eMax14830);
	  Max14830_EnableClk(eMax14830,u8_ch);	
	}
}

/* Max14830扩展串口相关操作结束 */

头文件如下：

/******************************************************************************
* 文 件  名 称:BspMax14830.h
* 文件功能概述:实现MAX14830驱动接口
* 文 件  作 者:   
* 版        本:V1.0.0.0
* 修 订  记 录:2018-4-28创建
******************************************************************************/

#ifndef __BSP_MAX14830_H__
#define __BSP_MAX14830_H__

#include "..\BspInterface.h"

#define MAX310X_DUMMY_BYTE    0xFF
/* MAX310X register definitions */
#define MAX310X_RHR_REG			(0x00) /* RX FIFO */
#define MAX310X_THR_REG			(0x00) /* TX FIFO */
#define MAX310X_IRQEN_REG		(0x01) /* IRQ enable */
#define MAX310X_IRQSTS_REG		(0x02) /* IRQ status */
#define MAX310X_LSR_IRQEN_REG		(0x03) /* LSR IRQ enable */
#define MAX310X_LSR_IRQSTS_REG		(0x04) /* LSR IRQ status */
#define MAX310X_REG_05			(0x05)
#define MAX310X_SPCHR_IRQEN_REG		MAX310X_REG_05 /* Special char IRQ en */
#define MAX310X_SPCHR_IRQSTS_REG	(0x06) /* Special char IRQ status */
#define MAX310X_STS_IRQEN_REG		(0x07) /* Status IRQ enable */
#define MAX310X_STS_IRQSTS_REG		(0x08) /* Status IRQ status */
#define MAX310X_MODE1_REG		(0x09) /* MODE1 */
#define MAX310X_MODE2_REG		(0x0a) /* MODE2 */
#define MAX310X_LCR_REG			(0x0b) /* LCR */
#define MAX310X_RXTO_REG		(0x0c) /* RX timeout */
#define MAX310X_HDPIXDELAY_REG		(0x0d) /* Auto transceiver delays */
#define MAX310X_IRDA_REG		(0x0e) /* IRDA settings */
#define MAX310X_FLOWLVL_REG		(0x0f) /* Flow control levels */
#define MAX310X_FIFOTRIGLVL_REG		(0x10) /* FIFO IRQ trigger levels */
#define MAX310X_TXFIFOLVL_REG		(0x11) /* TX FIFO level */
#define MAX310X_RXFIFOLVL_REG		(0x12) /* RX FIFO level */
#define MAX310X_FLOWCTRL_REG		(0x13) /* Flow control */
#define MAX310X_XON1_REG		(0x14) /* XON1 character */
#define MAX310X_XON2_REG		(0x15) /* XON2 character */
#define MAX310X_XOFF1_REG		(0x16) /* XOFF1 character */
#define MAX310X_XOFF2_REG		(0x17) /* XOFF2 character */
#define MAX310X_GPIOCFG_REG		(0x18) /* GPIO config */
#define MAX310X_GPIODATA_REG		(0x19) /* GPIO data */
#define MAX310X_PLLCFG_REG		(0x1a) /* PLL config */
#define MAX310X_BRGCFG_REG		(0x1b) /* Baud rate generator conf */
#define MAX310X_BRGDIVLSB_REG		(0x1c) /* Baud rate divisor LSB */
#define MAX310X_BRGDIVMSB_REG		(0x1d) /* Baud rate divisor MSB */
#define MAX310X_CLKSRC_REG		(0x1e) /* Clock source */
#define MAX310X_REG_1F			(0x1f)

#define MAX310X_REVID_REG		MAX310X_REG_1F /* Revision ID */

#define MAX310X_GLOBALIRQ_REG		MAX310X_REG_1F /* Global IRQ (RO) */
#define MAX310X_GLOBALCMD_REG		MAX310X_REG_1F /* Global Command (WO) */

/* Extended registers */
#define MAX310X_REVID_EXTREG		MAX310X_REG_05 /* Revision ID */

/* IRQ register bits */
#define MAX310X_IRQ_LSR_BIT		(1 << 0) /* LSR interrupt */
#define MAX310X_IRQ_SPCHR_BIT		(1 << 1) /* Special char interrupt */
#define MAX310X_IRQ_STS_BIT		(1 << 2) /* Status interrupt */
#define MAX310X_IRQ_RXFIFO_BIT		(1 << 3) /* RX FIFO interrupt */
#define MAX310X_IRQ_TXFIFO_BIT		(1 << 4) /* TX FIFO interrupt */
#define MAX310X_IRQ_TXEMPTY_BIT		(1 << 5) /* TX FIFO empty interrupt */
#define MAX310X_IRQ_RXEMPTY_BIT		(1 << 6) /* RX FIFO empty interrupt */
#define MAX310X_IRQ_CTS_BIT		(1 << 7) /* CTS interrupt */

/* LSR register bits */
#define MAX310X_LSR_RXTO_BIT		(1 << 0) /* RX timeout */
#define MAX310X_LSR_RXOVR_BIT		(1 << 1) /* RX overrun */
#define MAX310X_LSR_RXPAR_BIT		(1 << 2) /* RX parity error */
#define MAX310X_LSR_FRERR_BIT		(1 << 3) /* Frame error */
#define MAX310X_LSR_RXBRK_BIT		(1 << 4) /* RX break */
#define MAX310X_LSR_RXNOISE_BIT		(1 << 5) /* RX noise */
#define MAX310X_LSR_CTS_BIT		(1 << 7) /* CTS pin state */

/* Special character register bits */
#define MAX310X_SPCHR_XON1_BIT		(1 << 0) /* XON1 character */
#define MAX310X_SPCHR_XON2_BIT		(1 << 1) /* XON2 character */
#define MAX310X_SPCHR_XOFF1_BIT		(1 << 2) /* XOFF1 character */
#define MAX310X_SPCHR_XOFF2_BIT		(1 << 3) /* XOFF2 character */
#define MAX310X_SPCHR_BREAK_BIT		(1 << 4) /* RX break */
#define MAX310X_SPCHR_MULTIDROP_BIT	(1 << 5) /* 9-bit multidrop addr char */

/* Status register bits */
#define MAX310X_STS_GPIO0_BIT		(1 << 0) /* GPIO 0 interrupt */
#define MAX310X_STS_GPIO1_BIT		(1 << 1) /* GPIO 1 interrupt */
#define MAX310X_STS_GPIO2_BIT		(1 << 2) /* GPIO 2 interrupt */
#define MAX310X_STS_GPIO3_BIT		(1 << 3) /* GPIO 3 interrupt */
#define MAX310X_STS_CLKREADY_BIT	(1 << 5) /* Clock ready */
#define MAX310X_STS_SLEEP_BIT		(1 << 6) /* Sleep interrupt */

/* MODE1 register bits */
#define MAX310X_MODE1_RXDIS_BIT		(1 << 0) /* RX disable */
#define MAX310X_MODE1_TXDIS_BIT		(1 << 1) /* TX disable */
#define MAX310X_MODE1_TXHIZ_BIT		(1 << 2) /* TX pin three-state */
#define MAX310X_MODE1_RTSHIZ_BIT	(1 << 3) /* RTS pin three-state */
#define MAX310X_MODE1_TRNSCVCTRL_BIT	(1 << 4) /* Transceiver ctrl enable */
#define MAX310X_MODE1_FORCESLEEP_BIT	(1 << 5) /* Force sleep mode */
#define MAX310X_MODE1_AUTOSLEEP_BIT	(1 << 6) /* Auto sleep enable */
#define MAX310X_MODE1_IRQSEL_BIT	(1 << 7) /* IRQ pin enable */

/* MODE2 register bits */
#define MAX310X_MODE2_RST_BIT		(1 << 0) /* Chip reset */
#define MAX310X_MODE2_FIFORST_BIT	(1 << 1) /* FIFO reset */
#define MAX310X_MODE2_RXTRIGINV_BIT	(1 << 2) /* RX FIFO INT invert */
#define MAX310X_MODE2_RXEMPTINV_BIT	(1 << 3) /* RX FIFO empty INT invert */
#define MAX310X_MODE2_SPCHR_BIT		(1 << 4) /* Special chr detect enable */
#define MAX310X_MODE2_LOOPBACK_BIT	(1 << 5) /* Internal loopback enable */
#define MAX310X_MODE2_MULTIDROP_BIT	(1 << 6) /* 9-bit multidrop enable */
#define MAX310X_MODE2_ECHOSUPR_BIT	(1 << 7) /* ECHO suppression enable */

/* LCR register bits */
#define MAX310X_LCR_LENGTH0_BIT		(1 << 0) /* Word length bit 0 */
#define MAX310X_LCR_LENGTH1_BIT		(1 << 1) /* Word length bit 1
						  *
						  * Word length bits table:
						  * 00 -> 5 bit words
						  * 01 -> 6 bit words
						  * 10 -> 7 bit words
						  * 11 -> 8 bit words
						  */
#define MAX310X_LCR_STOPLEN_BIT		(1 << 2) /* STOP length bit
						  *
						  * STOP length bit table:
						  * 0 -> 1 stop bit
						  * 1 -> 1-1.5 stop bits if
						  *      word length is 5,
						  *      2 stop bits otherwise
						  */
#define MAX310X_LCR_PARITY_BIT		(1 << 3) /* Parity bit enable */
#define MAX310X_LCR_EVENPARITY_BIT	(1 << 4) /* Even parity bit enable */
#define MAX310X_LCR_FORCEPARITY_BIT	(1 << 5) /* 9-bit multidrop parity */
#define MAX310X_LCR_TXBREAK_BIT		(1 << 6) /* TX break enable */
#define MAX310X_LCR_RTS_BIT		(1 << 7) /* RTS pin control */
#define MAX310X_LCR_WORD_LEN_5		(0x00)
#define MAX310X_LCR_WORD_LEN_6		(0x01)
#define MAX310X_LCR_WORD_LEN_7		(0x02)
#define MAX310X_LCR_WORD_LEN_8		(0x03)

/* IRDA register bits */
#define MAX310X_IRDA_IRDAEN_BIT		(1 << 0) /* IRDA mode enable */
#define MAX310X_IRDA_SIR_BIT		(1 << 1) /* SIR mode enable */

/* Flow control trigger level register masks */
#define MAX310X_FLOWLVL_HALT_MASK	(0x000f) /* Flow control halt level */
#define MAX310X_FLOWLVL_RES_MASK	(0x00f0) /* Flow control resume level */
#define MAX310X_FLOWLVL_HALT(words)	((words / 8) & 0x0f)
#define MAX310X_FLOWLVL_RES(words)	(((words / 8) & 0x0f) << 4)

/* FIFO interrupt trigger level register masks */
#define MAX310X_FIFOTRIGLVL_TX_MASK	(0x0f) /* TX FIFO trigger level */
#define MAX310X_FIFOTRIGLVL_RX_MASK	(0xf0) /* RX FIFO trigger level */
#define MAX310X_FIFOTRIGLVL_TX(words)	((words / 8) & 0x0f)
#define MAX310X_FIFOTRIGLVL_RX(words)	(((words / 8) & 0x0f) << 4)

/* Flow control register bits */
#define MAX310X_FLOWCTRL_AUTORTS_BIT	(1 << 0) /* Auto RTS flow ctrl enable */
#define MAX310X_FLOWCTRL_AUTOCTS_BIT	(1 << 1) /* Auto CTS flow ctrl enable */
#define MAX310X_FLOWCTRL_GPIADDR_BIT	(1 << 2) /* Enables that GPIO inputs
						  * are used in conjunction with
						  * XOFF2 for definition of
						  * special character */
#define MAX310X_FLOWCTRL_SWFLOWEN_BIT	(1 << 3) /* Auto SW flow ctrl enable */
#define MAX310X_FLOWCTRL_SWFLOW0_BIT	(1 << 4) /* SWFLOW bit 0 */
#define MAX310X_FLOWCTRL_SWFLOW1_BIT	(1 << 5) /* SWFLOW bit 1
						  *
						  * SWFLOW bits 1 & 0 table:
						  * 00 -> no transmitter flow
						  *       control
						  * 01 -> receiver compares
						  *       XON2 and XOFF2
						  *       and controls
						  *       transmitter
						  * 10 -> receiver compares
						  *       XON1 and XOFF1
						  *       and controls
						  *       transmitter
						  * 11 -> receiver compares
						  *       XON1, XON2, XOFF1 and
						  *       XOFF2 and controls
						  *       transmitter
						  */
#define MAX310X_FLOWCTRL_SWFLOW2_BIT	(1 << 6) /* SWFLOW bit 2 */
#define MAX310X_FLOWCTRL_SWFLOW3_BIT	(1 << 7) /* SWFLOW bit 3
						  *
						  * SWFLOW bits 3 & 2 table:
						  * 00 -> no received flow
						  *       control
						  * 01 -> transmitter generates
						  *       XON2 and XOFF2
						  * 10 -> transmitter generates
						  *       XON1 and XOFF1
						  * 11 -> transmitter generates
						  *       XON1, XON2, XOFF1 and
						  *       XOFF2
						  */

/* PLL configuration register masks */
#define MAX310X_PLLCFG_PREDIV_MASK	(0x3f) /* PLL predivision value */
#define MAX310X_PLLCFG_PLLFACTOR_MASK	(0xc0) /* PLL multiplication factor */

/* Baud rate generator configuration register bits */
#define MAX310X_BRGCFG_2XMODE_BIT	(1 << 4) /* Double baud rate */
#define MAX310X_BRGCFG_4XMODE_BIT	(1 << 5) /* Quadruple baud rate */

/* Clock source register bits */
#define MAX310X_CLKSRC_CRYST_BIT	(1 << 1) /* Crystal osc enable */
#define MAX310X_CLKSRC_PLL_BIT		(1 << 2) /* PLL enable */
#define MAX310X_CLKSRC_PLLBYP_BIT	(1 << 3) /* PLL bypass */
#define MAX310X_CLKSRC_EXTCLK_BIT	(1 << 4) /* External clock enable */
#define MAX310X_CLKSRC_CLK2RTS_BIT	(1 << 7) /* Baud clk to RTS pin */

/* Global commands */
#define MAX310X_EXTREG_ENBL		(0xce)
#define MAX310X_EXTREG_DSBL		(0xcd)

/* Misc definitions */
#define MAX310X_FIFO_SIZE		(128)
#define MAX310x_REV_MASK		(0xfc)

/* MAX14830 specific */
#define MAX14830_BRGCFG_CLKDIS_BIT	(1 << 6) /* Clock Disable */
#define MAX14830_REV_ID			(0xb0)

#define Max14830_WRITE 0x80
#define Max14830_READ 0x00
	
typedef enum
{
  E_MAX14830_1,
  
  E_MAX14830_MAX,
  
  E_MAX14830_INVALID,
}E_MAX14830x;

sint32 Max14830xWriteBytes(E_MAX14830x eMax14830,uint8 u8_sub_ch, uint8_t *p_data, uint16_t u16_len);
sint32 Max14830xReadBytes(E_MAX14830x eMax14830,uint8 u8_sub_ch, uint8_t *p_data, uint16_t u16_len);

sint8 Max14830_Init(E_MAX14830x eMax14830);

void Max14830_ResetModule(E_MAX14830x eMax14830, uint8 u8_ch);

#endif

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STM32之MAX14830

驱动如下：/******************************************************************************* 文件名称:BspMax14830.c* 文件功能概述:实现MAX14830驱动接口* 文件作者: * 版本:V1.0.0.0* 修订记录:2018-4-28创建***...
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