qq_18553915的博客

Python for Data Analysis 2nd Edition，内部有kindle版本和PDF版本，都是非扫描高清版本

简明Python教程，或者叫byte-of-python-chinese-edition，kindle版的和pdf都有

3GPP标准制定是高度系统化的程序，从规范筹备、格式内容到制定程序等都有一套严谨的步骤和规范，以确保标准的一致性和公信力。每一份文件都要经过数次改版（变更请求，CR），每次发布一个版本标准里面包含了数百件技术规范（Technique Specification, TS）和技术报告（Technique Report, TR）

Abstract—Low-Density Parity Check (LDPC) error correction decoders have become popular in communications systems, as a benefit of their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into LDPC decoder designs that exploit the flexibility, the high processing speed and the parallelism of Field-Programmable Gate Array (FPGA) devices. FPGAs are ideal for design prototyping and for the manufacturing of small-production-run devices, where their insystem programmability makes them far more cost-effective than Application-Specific Integrated Circuits (ASICs). However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare. This paper explores the key factors involved in FPGA-based LDPC decoder design and presents an extensive review of the current literature. In-depth comparisons are drawn amongst 140 published designs (both academic and industrial) and the associated performance trade-offs are characterised, discussed and illustrated. Seven key performance characteristics are described, namely their processing throughput, processing latency, hardware resource requirements, error correction capability, processing energy efficiency, bandwidth efficiency and flexibility. We offer recommendations that will facilitate fairer comparisons of future designs, as well as opportunities for improving the design of FPGA-based LDPC decoders.

zedboard 开发板的SD卡镜像，2014.4-release.tar.xz2014.