序列检测器

序列检测器

module seqdet(nrst,clk,cin,cout,num);
input nrst,clk;
 input cin;
 output cout;
 output [7:0]num;
 reg cout;
 reg [7:0]num;
 reg [4:0]CS,NS;
 parameter [4:0] IDLE=5'b00000, A=5'b00001,B=5'b00010,C=5'b00100, D=5'b01000,E=5'b10000,F=5'b11000,G=5'b10100;
always @(posedge clk or negedge nrst)
         begin
if(!nrst)
CS <= IDLE;
else
CS <= NS;
end
always @( CS or cin)
begin
   case(CS)   
IDLE: begin if(cin==1)  NS=A; else NS=IDLE;end
A:begin  if(cin==0) NS=B; else NS=A; end
B:begin if(cin==1) NS=C; else NS=IDLE;end
C:begin if(cin==1) NS=D; else NS=B; end
D:begin if(cin==0) NS=E; else NS=A;end
   E:begin if(cin==0) NS=F; else NS=C;end
F:begin if(cin==1) NS=G; else NS=IDLE;end
G:begin if(cin==0) NS=B; else NS=A;end
   default:NS=IDLE;
endcase 
end
always @(CS) 
begin  
case(CS)
IDLE,A,B,C,D,E,F: cout<=0;  
G:cout<=1;  
default:cout<=0;  
endcase 
end  
always@(posedge cout)
num<=num+1;
endmodule