stm32H743在汇编启动文件中直接卡死问题
背景
移植chibios6.1版本到stm32h743芯片上，由于chibios的启动文件与其链接脚本是配合使用的，如：
- 中断向量表以数字命名而非st那样的以中断名称命名，启动文件是自带的。
- 堆的大小是在链接脚本中分配好，并定义好堆的地址符号及空间符号。
- MSP和PSP是在调用链接器时临时传入的而非在链接脚本中设置的(为了方便脚本设置主堆栈和进程堆栈大小)。
所以无法使用诸如stm32cubemx生成或st厂家提供的.S汇编启动文件。
实际使用的是chibios自带的三个.S文件
ChibiOS/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S ChibiOS/os/common/startup/ARMCMx/compilers/GCC/vectors.S ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S
- crt0_v7m.S：编写了很多初始化函数，如_crt0_entry，msloop，psloop。就是st官方启动文件中Reset_Handler的作用。
- vectors.S定义了中断向量表。
- chcoreasm_v7m.S：编写了chibios的核心调度部分的汇编代码。
而问题就发生在crt0_v7m.S中。
下面附上代码
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file crt0_v7m.S
* @brief Generic ARMv7-M (Cortex-M3/M4/M7) startup file for ChibiOS.
*
* @addtogroup ARMCMx_GCC_STARTUP_V7M
* @{
*/
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
#if !defined(FALSE) || defined(__DOXYGEN__)
#define FALSE 0
#endif
#if !defined(TRUE) || defined(__DOXYGEN__)
#define TRUE 1
#endif
#define CONTROL_MODE_PRIVILEGED 0
#define CONTROL_MODE_UNPRIVILEGED 1
#define CONTROL_USE_MSP 0
#define CONTROL_USE_PSP 2
#define CONTROL_FPCA 4
#define FPCCR_ASPEN (1 << 31)
#define FPCCR_LSPEN (1 << 30)
#define SCB_VTOR 0xE000ED08
#define SCB_CPACR 0xE000ED88
#define SCB_FPCCR 0xE000EF34
#define SCB_FPDSCR 0xE000EF3C
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/**
* @brief Enforces initialization of MSP.
* @note This is required if the boot process is not reliable for whatever
* reason (bad ROMs, bad bootloaders, bad debuggers=.
*/
#if !defined(CRT0_FORCE_MSP_INIT) || defined(__DOXYGEN__)
#define CRT0_FORCE_MSP_INIT TRUE
#endif
/**
* @brief VTOR special register initialization.
* @details VTOR is initialized to point to the vectors table.
*/
#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
#define CRT0_VTOR_INIT TRUE
#endif
/**
* @brief FPU initialization switch.
*/
#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__)
#define CRT0_INIT_FPU CORTEX_USE_FPU
#else
#define CRT0_INIT_FPU FALSE
#endif
#endif
/**
* @brief Control special register initialization value.
* @details The system is setup to run in privileged mode using the PSP
* stack (dual stack mode).
*/
#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
CONTROL_MODE_PRIVILEGED)
#endif
/**
* @brief Core initialization switch.
*/
#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
#define CRT0_INIT_CORE TRUE
#endif
/**
* @brief Stack segments initialization switch.
*/
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
#define CRT0_STACKS_FILL_PATTERN 0x55555555
#endif
/**
* @brief Stack segments initialization switch.
*/
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
#define CRT0_INIT_STACKS TRUE
#endif
/**
* @brief DATA segment initialization switch.
*/
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
#define CRT0_INIT_DATA TRUE
#endif
/**
* @brief BSS segment initialization switch.
*/
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
#define CRT0_INIT_BSS TRUE
#endif
/**
* @brief RAM Functions initialization switch.
*/
#if !defined(CRT0_INIT_RAMFUNCS) || defined(__DOXYGEN__)
#define CRT0_INIT_RAMFUNCS TRUE
#endif
/**
* @brief RAM areas initialization switch.
*/
#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
#define CRT0_INIT_RAM_AREAS TRUE
#endif
/**
* @brief Constructors invocation switch.
*/
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
#define CRT0_CALL_CONSTRUCTORS TRUE
#endif
/**
* @brief Destructors invocation switch.
*/
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
#define CRT0_CALL_DESTRUCTORS TRUE
#endif
/**
* @brief FPU FPCCR register initialization value.
* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
*/
#if !defined(CRT0_FPCCR_INIT) || defined(__DOXYGEN__)
#define CRT0_FPCCR_INIT (FPCCR_ASPEN | FPCCR_LSPEN)
#endif
/**
* @brief CPACR register initialization value.
* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
*/
#if !defined(CRT0_CPACR_INIT) || defined(__DOXYGEN__)
#define CRT0_CPACR_INIT 0x00F00000
#endif
/*===========================================================================*/
/* Code section. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
.syntax unified
.cpu cortex-m3
#if CRT0_INIT_FPU == TRUE
.fpu fpv4-sp-d16
#else
.fpu softvfp
#endif
.thumb
.text
/*
* CRT0 entry point.
*/
.align 2
.thumb_func
.global _crt0_entry
_crt0_entry:
/* Interrupts are globally masked initially.*/
cpsid i
#if CRT0_FORCE_MSP_INIT == TRUE
/* MSP stack pointers initialization.*/
ldr r0, =__main_stack_end__
msr MSP, r0
#endif
/* PSP stack pointers initialization.*/
ldr r0, =__process_stack_end__
msr PSP, r0
#if CRT0_VTOR_INIT == TRUE
ldr r0, =_vectors
movw r1, #SCB_VTOR & 0xFFFF
movt r1, #SCB_VTOR >> 16
str r0, [r1]
#endif
#if CRT0_INIT_FPU == TRUE
/* FPU FPCCR initialization.*/
movw r0, #CRT0_FPCCR_INIT & 0xFFFF
movt r0, #CRT0_FPCCR_INIT >> 16
movw r1, #SCB_FPCCR & 0xFFFF
movt r1, #SCB_FPCCR >> 16
str r0, [r1]
dsb
isb
/* CPACR initialization.*/
movw r0, #CRT0_CPACR_INIT & 0xFFFF
movt r0, #CRT0_CPACR_INIT >> 16
movw r1, #SCB_CPACR & 0xFFFF
movt r1, #SCB_CPACR >> 16
str r0, [r1]
dsb
isb
/* FPU FPSCR initially cleared.*/
mov r0, #0
vmsr FPSCR, r0
/* FPU FPDSCR initially cleared.*/
movw r1, #SCB_FPDSCR & 0xFFFF
movt r1, #SCB_FPDSCR >> 16
str r0, [r1]
/* Enforcing FPCA bit in the CONTROL register.*/
movs r0, #CRT0_CONTROL_INIT | CONTROL_FPCA
#else
movs r0, #CRT0_CONTROL_INIT
#endif
/* CONTROL register initialization as configured.*/
msr CONTROL, r0
isb
#if CRT0_INIT_RAMFUNCS == TRUE
bl __init_ramfunc_area
#endif
#if CRT0_INIT_CORE == TRUE
/* Core initialization.*/
bl __core_init
#endif
/* Early initialization.*/
bl __early_init
#if CRT0_INIT_STACKS == TRUE
ldr r0, =CRT0_STACKS_FILL_PATTERN
/* Main Stack initialization. Note, it assumes that the
stack size is a multiple of 4 so the linker file must
ensure this.*/
ldr r1, =__main_stack_base__
ldr r2, =__main_stack_end__
msloop:
cmp r1, r2
itt lo
strlo r0, [r1], #4
blo msloop
/* Process Stack initialization. Note, it assumes that the
stack size is a multiple of 4 so the linker file must
ensure this.*/
ldr r1, =__process_stack_base__
ldr r2, =__process_stack_end__
psloop:
cmp r1, r2
itt lo
strlo r0, [r1], #4
blo psloop
#endif
#if CRT0_INIT_DATA == TRUE
/* Data initialization. Note, it assumes that the DATA size
is a multiple of 4 so the linker file must ensure this.*/
ldr r1, =__textdata_base__
ldr r2, =__data_base__
ldr r3, =__data_end__
dloop:
cmp r2, r3
ittt lo
ldrlo r0, [r1], #4
strlo r0, [r2], #4
blo dloop
#endif
#if CRT0_INIT_BSS == TRUE
/* BSS initialization. Note, it assumes that the DATA size
is a multiple of 4 so the linker file must ensure this.*/
movs r0, #0
ldr r1, =__bss_base__
ldr r2, =__bss_end__
bloop:
cmp r1, r2
itt lo
strlo r0, [r1], #4
blo bloop
#endif
#if CRT0_INIT_RAM_AREAS == TRUE
/* RAM areas initialization.*/
bl __init_ram_areas
#endif
/* Late initialization..*/
bl __late_init
#if CRT0_CALL_CONSTRUCTORS == TRUE
/* Constructors invocation.*/
ldr r4, =__init_array_base__
ldr r5, =__init_array_end__
initloop:
cmp r4, r5
bge endinitloop
ldr r1, [r4], #4
blx r1
b initloop
endinitloop:
#endif
/* Main program invocation, r0 contains the returned value.*/
bl main
#if CRT0_CALL_DESTRUCTORS == TRUE
/* Destructors invocation.*/
ldr r4, =__fini_array_base__
ldr r5, =__fini_array_end__
finiloop:
cmp r4, r5
bge endfiniloop
ldr r1, [r4], #4
blx r1
b finiloop
endfiniloop:
#endif
/* Branching to the defined exit handler.*/
b __default_exit
#endif /* !defined(__DOXYGEN__) */
/** @} */
问题描述
芯片复位时第一条指令就是跳转到_crt0_entry函数，卡死的地方在__core_init函数。可知从上电到卡死也就只运行了下面这几十条汇编代码:
_crt0_entry:
/* Interrupts are globally masked initially.*/
cpsid i
#if CRT0_FORCE_MSP_INIT == TRUE
/* MSP stack pointers initialization.*/
ldr r0, =__main_stack_end__
msr MSP, r0
#endif
/* PSP stack pointers initialization.*/
ldr r0, =__process_stack_end__
msr PSP, r0
#if CRT0_VTOR_INIT == TRUE
ldr r0, =_vectors
movw r1, #SCB_VTOR & 0xFFFF
movt r1, #SCB_VTOR >> 16
str r0, [r1]
#endif
#if CRT0_INIT_FPU == TRUE
/* FPU FPCCR initialization.*/
movw r0, #CRT0_FPCCR_INIT & 0xFFFF
movt r0, #CRT0_FPCCR_INIT >> 16
movw r1, #SCB_FPCCR & 0xFFFF
movt r1, #SCB_FPCCR >> 16
str r0, [r1]
dsb
isb
/* CPACR initialization.*/
movw r0, #CRT0_CPACR_INIT & 0xFFFF
movt r0, #CRT0_CPACR_INIT >> 16
movw r1, #SCB_CPACR & 0xFFFF
movt r1, #SCB_CPACR >> 16
str r0, [r1]
dsb
isb
/* FPU FPSCR initially cleared.*/
mov r0, #0
vmsr FPSCR, r0
/* FPU FPDSCR initially cleared.*/
movw r1, #SCB_FPDSCR & 0xFFFF
movt r1, #SCB_FPDSCR >> 16
str r0, [r1]
/* Enforcing FPCA bit in the CONTROL register.*/
movs r0, #CRT0_CONTROL_INIT | CONTROL_FPCA
#else
movs r0, #CRT0_CONTROL_INIT
#endif
/* CONTROL register initialization as configured.*/
msr CONTROL, r0
isb
#if CRT0_INIT_RAMFUNCS == TRUE
bl __init_ramfunc_area
#endif
#if CRT0_INIT_CORE == TRUE
/* Core initialization.*/
bl __core_init
而这些代码仔细看了一下就是正常的设置堆栈指针，中断向量表和fpu等。__core_init函数代码如下，只干了两件事，就是使能ICache和DCache。第一条函数正常运行，在运行到SCB_EnableDCache()结束时跳入hardfault。
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
void __core_init(void) {
#if CORTEX_MODEL == 7
SCB_EnableICache();
SCB_EnableDCache();
#endif
}
再贴上SCB_EnableDCache()，该函数是arm官方写的，在ChibiOS/os/common/ext/ARM/CMSIS/Core/Include/core_cm7.h文件中，按说不可能出错。
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_INLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
好在有一版可以正常运行的代码做对比。对比观察区别如下：
正常运行时 SCB->CCSIDR寄存器中的值为0xf00fe019
而我的代码运行到此处时SCB->CCSIDR寄存器中的值为没有直接查看，而是看的ccsidr这个变量，这个变量值为0
在单步调试到此处时起初由于设置的编译参数为-O0 -g2，所以gdb无法查看到SCB寄存器的值，所以以为SCB->CCSIDR寄存器中的值就是为0。于是定位问题在使能DCache前的其它操作不正确导致SCB->CCSIDR寄存器中的值异常。苦苦搜寻一天无果。最后实在没辙了，没有一点头绪了。正恍惚间想仔细看看这个寄存器的值，于是修改编译参数-g2为-g3，此时运行到此处查看寄存器的值
发现SCB->CCSIDR寄存器中的值实际上是正常的而变量ccsidr却为0.由于后续的操作全都是以ccsidr变量的值来进行的，所以导致异常。
解决办法
瞬间就能想到是由于编译优化导致的问题，于是将编译参数-O0改为-Og，再次编译运行到此处发现
此时变量ccsidr与SCB->CCSIDR寄存器中的值一致。运行正常，问题解决。
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