// -------------------------------------------------------------------------------------------------------
// USER ADDRESS:
// -------------------------------------------------------------------------------------------------------
// ___________________________________________________________________________
// Counter Reconfig | is_dps | is_counter | M/N/C ID | C COUNTER INDEX |
// | 1'b0 | 1'b1 | 3'b | 4'b |
// |---------------+---------------+-----------------------+-------------------|
// DPS Reconfig | is_dps | is_counter | RSVD | C COUNTER INDEX |
// | 1'b1 | 0'b1 | 3'b | 4'b |
// |---------------+---------------+-----------------------+-------------------|
// Analog Reconfig | is_dps | is_counter | BW/CP ID | RSVD |
// | 1'b0 | 1'b0 | 3'b | 4'b |
// |---------------+---------------+-----------------------+-------------------|
// MIF Streaming | is_dps | is_counter | START_MIF ID | RSVD |
// | 1'b0 | 1'b0 | 3'b | 4'b |
// |---------------+---------------+-----------------------+-------------------|
// Generic Reconfig | is_dps | is_counter | DPRIO_ADDRESS |
// | 1'b | 1'b | 7'b |
// '---------------'---------------'-------------------------------------------'
//
// -----------------
// Analog Reconfig
// -----------------
// BW/CP ID :
// - BW = 3'b100
// - CP = 3'b010
//
// -------------------------------------------------------------------------------------------------------
// USER DATA:
// -------------------------------------------------------------------------------------------------------
//
// Counter:
// | odd_duty_en | bypass_enable | hi7 .. hi0 | lo7 .. lo0 |
// | 17 | 16 | 15 .. 8 | 7 .. 0 |
// DPS:
// | RSVD | up_dn | num_phase_shifts |
// | 17 .. 4 | 3 | 2 .. 0 |
//
//
// -------------------------------------------------------------------------------------------------------
// USER DATA:
// -------------------------------------------------------------------------------------------------------
// ___________________________________________________________________________
// Counter Reconfig | odd_duty_en | bypass_en | hi_div[7:0] | lo_div[7:0] |
// | 17 | 16 | 15 .. 8 | 7 .. 0 |
// '-------------+-------------+-----------------------+-----------------------'
// ___________________________________________________________________________
// DPS Reconfig | RSVD | up_dn | num_phase_shifts |
// | 17 .. 4 | 3 | 2 .. 0 |
// '--------------------------------------------+-----------+------------------'
// ___________________________________________________________________________
// Analog Reconfig | RSVD | bw_ctrl | cp_current |
// | 17 .. 10 | 9 .. 6 | 5 .. 0 |
// '-------------------------------------+----------------+--------------------'
// ___________________________________________________________________________
// Generic Reconfig | RSVD | DPRIO data |
// | 17 .. 8 | 7 .. 0 |
// '--------------------------------------------+------------------------------'
//
// -------------------------------------------------------------------------------------------------------
// DPRIO LATENCIES
// -------------------------------------------------------------------------------------------------------
// READ Latencies:
// readWaitTime = 0 (# of extra cycles to hold read high after captured)
// readLatency = 2 (# of cycles for valid data)
// _______
// Read: ___| |_______________________
// ___ ___ ___ ___
// CLK: ___| |___| |___| |___| |___
//
// CYCLE: | 0 | 1 | 2 |
// ________________
// DPRIO READDATA: ___________________| DATAOUT
//
// WRITE Latencies:
// writeWaitTime = 0 (one/current cycle write assert sufficient)
// writelatency = n/a (meaningless, we're not getting data back)
//
// -------------------------------------------------------------------------------------------------------
代码中优美的注释
最新推荐文章于 2022-11-08 21:13:23 发布