PWM(一) A133 Android10 Linux-4.9 S_PWM无波形

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已于 2024-08-12 11:39:52 修改

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分类专栏：全志A133 文章标签： s_pwm Android 10 A133

于 2024-08-12 10:33:42 首次发布

本文链接：https://blog.csdn.net/qq_38173035/article/details/141124950

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A133 Android10 Linux-4.9 S_PWM无波形

补丁

device目录补丁

diff --git a/configs/b7/board.dts b/configs/b7/board.dts
--- a/configs/b7/board.dts
+++ b/configs/b7/board.dts
@@ -47,6 +47,23 @@
 				allwinner,drive = <1>;
 				allwinner,pull = <1>;
 			};
+
+			s_pwm0_pin_a: s_pwm0@0 {
+                                allwinner,pins = "PL10";
+                                allwinner,function = "s_pwm0";
+                                allwinner,muxsel = <0x02>;
+                                allwinner,drive = <0x2>;
+                                allwinner,pull = <0>;
+                                allwinner,data = <0xffffffff>;
+                        };
+
+                        s_pwm0_pin_b: s_pwm0@1 {
+                                allwinner,pins = "PL10";
+                                allwinner,function = "io_disabled";
+                                allwinner,muxsel = <0x07>;
+                                allwinner,pull = <0>;
+                                allwinner,data = <0xffffffff>;
+                        };
 		};
 		pio: pinctrl@0300b000 {
 			twi0_pins_a: twi0@0 {
@@ -737,6 +754,13 @@
 			pinctrl-1 = <&pwm0_pin_b>;
 		};
 
+		s_pwm0: s_pwm0@7020c10 {
+			pinctrl-names = "active", "sleep";
+			pinctrl-0 = <&s_pwm0_pin_a>;
+			pinctrl-1 = <&s_pwm0_pin_b>;
+			status = "okay";
+		};
+
 		spi0: spi@05010000 {
 			pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
 			pinctrl-1 = <&spi1_pins_c>;

diff --git a/arch/arm64/boot/dts/sunxi/sun50iw10p1-clk.dtsi 
--- a/arch/arm64/boot/dts/sunxi/sun50iw10p1-clk.dtsi
+++ b/arch/arm64/boot/dts/sunxi/sun50iw10p1-clk.dtsi
@@ -548,6 +548,12 @@ clocks {
 			compatible = "allwinner,periph-clock";
 			clock-output-names = "twi1";
 		};
+		clk_spwm: spwm {
+			#clock-cells = <0>;
+			compatible = "allwinner,periph-cpus-clock";
+			clock-output-names = "spwm";
+
+		};
 		clk_stwi0: stwi0 {
 			#clock-cells = <0>;
 			compatible = "allwinner,periph-cpus-clock";
diff --git a/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi 
--- a/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
+++ b/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
@@ -57,6 +57,8 @@
 		lcd0 = &lcd0;
 		lcd1 = &lcd1;
 		pwm = &pwm;
+		s-pwm = &s_pwm;
+		s-pwm0 = &s_pwm0;
 		pwm0 = &pwm0;
 		pwm1 = &pwm1;
 		pwm2 = &pwm2;
@@ -1591,6 +1593,21 @@
 				<&pwm10>, <&pwm11>, <&pwm12>, <&pwm13>,
 				<&pwm14>, <&pwm15>;
 		};
+		
+		s_pwm: s_pwm@7020c0000 {
+                        compatible = "allwinner,sunxi-pwm";
+                        reg = <0x0 0x07020c00 0x0 0x400>;
+                        clocks = <&clk_spwm>;
+                        pwm-number = <1>;
+                        pwm-base = <0x10>;
+                        pwms = <&s_pwm0>;
+                };
+
+		s_pwm0: s_pwm0@7020c10 {
+			compatible = "allwinner,sunxi-pwm16";
+			reg = <0x0 0x07020c10 0x0 0x4>;
+			reg_base = <0x07020c00>;
+		};
 
 		pwm0: pwm0@0300a000 {
 			compatible = "allwinner,sunxi-pwm0";
diff --git a/drivers/clk/sunxi/clk-sun50iw10.c b/drivers/clk/sunxi/clk-sun50iw10.c
--- a/drivers/clk/sunxi/clk-sun50iw10.c
+++ b/drivers/clk/sunxi/clk-sun50iw10.c
@@ -482,6 +482,7 @@ static const char *cpurpio_parents[] = {"cpurapbs1"};
 static const char *losc_parents[] = {"losc"};
 static const char *ledc_parents[] = {"hosc", "pll_periph0"};
 static const char *dcxo_parents[] = {"hosc"};
+static const char *spwm_parents[] = {"hosc", "losc", "iosc", ""};
 static const char *stwi_parents[] = {"cpurapbs1"};
 static const char *ppu_parents[] = {"cpurapbs1"};
 static const char *hosc32k_parents[] = {"hoscdiv32k"};
@@ -551,6 +552,7 @@ SUNXI_CLK_PERIPH(twi2,           0,               0,       0,            0,
 SUNXI_CLK_PERIPH(twi3,           0,               0,       0,            0,                  0,         0,          0,          0,          0,          0,               TWI_GATE,       TWI_GATE,           0,         0,          19,         3,             0,             &clk_lock, NULL,             0);
 SUNXI_CLK_PERIPH(twi4,           0,               0,       0,            0,                  0,         0,          0,          0,          0,          0,               TWI_GATE,       TWI_GATE,           0,         0,          20,         4,             0,             &clk_lock, NULL,             0);
 SUNXI_CLK_PERIPH(twi5,           0,               0,       0,            0,                  0,         0,          0,          0,          0,          0,               TWI_GATE,       TWI_GATE,           0,         0,          21,         5,             0,             &clk_lock, NULL,             0);
+SUNXI_CLK_PERIPH(spwm,           CPUS_PWM_CFG,   24,       2,            0,                  0,         0,          0,          0,          0,CPUS_PWM_CFG,               CPUS_PWM_GATE,   CPUS_PWM_GATE,    0,        31,          16,         0,             0,             &clk_lock, NULL,             0);
 SUNXI_CLK_PERIPH(stwi0,           0,               0,       0,            0,                  0,         0,          0,          0,          0,          0,               CPUS_TWI_GATE,   CPUS_TWI_GATE,     0,        0,          16,         0,             0,             &clk_lock, NULL,             0);
 SUNXI_CLK_PERIPH(stwi1,           0,               0,       0,            0,                  0,         0,          0,          0,          0,          0,               CPUS_TWI_GATE,   CPUS_TWI_GATE, 0,             0,          17,         1,             0,             &clk_lock, NULL,             0);
 SUNXI_CLK_PERIPH(scr0,           0,               0,       0,            0,                  0,         0,          0,          0,          0,          0,               SCR_GATE,       SCR_GATE,           0,         0,          16,         0,             0,             &clk_lock, NULL,             0);
@@ -735,6 +737,7 @@ struct periph_init_data sunxi_periphs_cpus_init[] = {
 	{"dcxo_out",        0,                                  dcxo_parents,           ARRAY_SIZE(dcxo_parents),           &sunxi_clk_periph_dcxo_out      },
 	{"hosc32k",         0,                                  hosc32k_parents,        ARRAY_SIZE(hosc32k_parents),       &sunxi_clk_periph_hosc32k       },
 	{"suart",           0,                                  apbs2mod_parents,       ARRAY_SIZE(apbs2mod_parents),       &sunxi_clk_periph_suart         },
+	{"spwm",            0,                                  spwm_parents,           ARRAY_SIZE(spwm_parents),           &sunxi_clk_periph_spwm          },
 	{"stwi0",            0,                                  stwi_parents,           ARRAY_SIZE(stwi_parents),           &sunxi_clk_periph_stwi0          },
 	{"stwi1",            0,                                  stwi_parents,           ARRAY_SIZE(stwi_parents),           &sunxi_clk_periph_stwi1          },
 	{"ppu",             0,                                  ppu_parents,            ARRAY_SIZE(ppu_parents),            &sunxi_clk_periph_ppu            },
diff --git a/drivers/clk/sunxi/clk-sun50iw10.h b/drivers/clk/sunxi/clk-sun50iw10.h
--- a/drivers/clk/sunxi/clk-sun50iw10.h
+++ b/drivers/clk/sunxi/clk-sun50iw10.h
@@ -162,6 +162,8 @@
 #define CPUS_APBS1_CFG      0x000C
 #define CPUS_APBS2_CFG      0x0010
 #define CPUS_TWDOG_GATE     0x012C
+#define CPUS_PWM_CFG	    0x0130
+#define CPUS_PWM_GATE       0x013C
 #define CPUS_PPU_GATE       0x017C
 #define CPUS_UART_GATE	    0x018C
 #define CPUS_TWI_GATE       0x019C