CS152 Review--Complex Pipelining

1.This problem deals with an out-of-order single-issue processor that is based on the basic RISC-V pipeline and has a floating-point unit. The FPU has one adder, one multiplier, and one load/store unit. The adder has a two-cycle latency and is fully pipelined. The multiplier has a six-cycle latency and is fully pipelined. Assume thatstores take one cycle and loads take two cycles.

There are 31 integer registers (x1-x32) and 32 floating-point registers (f0-f31). To maximize number of instructions that can be in the pipeline, register renaming is used. The decode stage can add up to one instruction per cycle to the re-order buffer (ROB). The CPU uses a data-in-ROB design, so there is one rename register associated with each ROB entry. Functional units write back to the ROB upon completion. The functional units share a single write port to the ROB. In the case of a write-back conflict, the older instruction writes back first. The instructions are committed in order and only one instruction may be committed per cycle. The earliest time an instruction can be committed is one cycle after write back.

Floating-point instructions (including loads writing floating-point registers) must spend one cycle in the write-back stage before theirresult can be used. Integer results are available for bypass the nextcycle after issue and write back two cycles after issue.

For the following questions, we will evaluate the performance of the code segment below.

Sequence	Instruction
$I_1$	FLD f1,0(x1)
$I_2$	FMUL.D f2,f1,f0
$I_3$	FADD.D f3,f2,f0
$I_4$	ADDI x1,x1,8
$I_5$	FLD f1,0(x1)
$I_6$	FMUL.D f2,f1,f1
$I_7$	FADD.D f2,f2,f3

(a)For this part, consider an ideal case where we have an unlimited number of ROB entries.
In the table below, fill in the cycle number for when each instruction enters the ROB, issues, writes back, and commits.Also, fill in the new register names for each instruction, where applicable. (10 points)
Since we have an infinite supply of register names, you should use a new register name for each register that is written (p0, p1, … ). Keep in mind that after a register has been renamed, subsequent instructions that refer to that register must refer to the new register name.

Answer: