verilog基础

Combinational Logic

Verilog Modules and Instantiation

• port declarations (input,output, or inout)
• Verilog has two types of net: wire(to connect inputs to outputs and for continuous assignment) and reg(when a net must preserve state)

  wire a;
  wire [7:0] d; // 8-bit wire declaration
  
  reg x;
  // A memory structure that has an array of 8 elements, where each element is a 32 bit number.
  reg [31:0] fifo_ram [7:0];
  fifo_ram[2] // The full 3rd 32-bit element
  fifo_ram[5][7:0] // The lowest byte of the 6th 32-bit element
  

• built in gates(and, or, xor, not, nand, nor, xnor)
  

Modules can be instantiated inside other modules. The syntax
used is

<module name> <instance name> (.port0(wire),.port1(wire), ...)
<module name> <instance name> (wire1,wire2, ...)

Verilog Operators & Logic Values

wire [7:0] d;
wire [31:0] e;
wire [31:0] f;
assign f = {d, e[23:0]}; // Concatenation + Slicing
assign f = { 32{d[5]} }; // Replication + Indexing

Continuous& Non-Continuous Assignment Examples

Continuous Assignment

Verilog Literals

• [bit width]’[radix][literal]
• radix (d,h,o,b)

If a signal is assigned using a continuous assignment statement, it must be declared as a wire.

Non-Continuous Assignment

Only reg nets can be assigned in an always block


Adder Generator
begin:name of this loop

module adder #(parameter width=32)
(input [width-1:0] a,
input [width-1:0] b,
output [width:0] s);
s = a + b;
endmodule

module top();
localparam adder1width = 64;
localparam adder2width = 32;
reg [adder1width-1:0] a,b;
reg [adder2width-1:0] c,d;
wire [adder1width:0] out1;
wire [adder2width:0] out2;
adder #(.width(adder1width)) adder64 (.a(a), .b(b), .s(out1));
adder #(.width(adder2width)) adder32 (.a(c), .b(d), .s(out2));
endmodule

Sequential Logic

Latch vs Flip-Flop

Use Nonblocking for Sequential Logic

Initial Blocks and Test Benches

Initial blocks are primarily used for test benches.

They contain sequences of code to be executed at the beginning of the simulation.

The delay operator (#) and at operator (@) are used in
the inital block to step through time events