下降沿计数器
代码;module neg_count(
input clk,
input rst,
output [7:0] data
);
reg [7:0] count ;
always @(negedge clk)
if(rst)
count = 0;
else
count =count+1’b1;
assign data=count;
endmodule
激励文件:
module neg_count_tb;
reg clk;
reg rst;
wire [7:0] data;
neg_count U1(.clk(clk),
.rst(rst),
.data(data));
always #10 clk=~clk;
initial begin
clk=0;
rst=1;
#100
rst= 0;
endendmodule
在这里插入图片描述