问题背景
LS1028原生支持两路uart和六路lpuart,OK1028A-C底板上只用了两路uart,客户在实际的应用中发现串口太少,就想使用lpuart串口。
分析思路
在原厂资料的《LSDKUG_Rev20.4.pdf》有关于LPUART的配置说明,参照里面的说明进行配置
1.需要在uboot中配置以下编译选项
配置文件路径packages/firmware/u-boot/configs/ls1028ardb_tfa_defconfig,添加:
CONFIG_LPUART=y
CONFIG_FSL_LPUART=y
CONFIG_LPUART_32B_REG=y
2. 内核配置
内核配置文件路径:packages/linux/linux/arch/arm64/configs/ok1028_defconfig
3.修改RCW
RCW路径:OK1028-linux-fs/packages/firmware/rcw/ls1028ardb/R_SQPP_0x85bb/rcw_1500_gpu600.rcw
将引脚复用为lpuart1、lpuart2,飞凌默认将lpuart1引脚用作了can1_rx/tx,lpuart2用作gpio
IIC3_PMUX=3
XSPI1_A_DATA74_PMUX=3
4.设备树绑定
设备树dtsi路径:OK1028-linux-fs/packages/linux/linux/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
添加lpuart设备节点:
lpuart0: serial@2260000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2260000 0x0 0x1000>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
clock-names = "ipg";
fsl,lpuart32;
status = "okay";
};
lpuart1: serial@2270000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2270000 0x0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
fsl,lpuart32;
status = "okay";
};
5.验证
全编译烧写到板子上,可以看到生成了lpuart1、lpuart2的设备节点分别为ttyLP0、ttyLP1
其他
添加的设备节点分析
分析:
1)reg :
LPUART1 base address: 226_0000h
LPUART2 base address: 227_0000h
2)Interrupts中断:(参考链接:http://www.lujun.org.cn/?p=3834)
1028使用的SPI:(shared peripheral interrupt),共享外设中断,该中断来源于外设,但是该中断可以对所有的core有效。
在CPU手册里面查看LPUART的中断号为264,但设备树里面是从0开始的,故要减32,所以为232
3) clocks
LPUART参考时钟,LPUART1时钟参考源为系统参考时钟,根据clockgen参考时钟的定义
设备树里面用的参考时钟
clockgen的定义:/Documentation/devicetree/binding/clock/qoriq-clock.txt
可以看到时钟参考源的选择
lpuart设备树节点定义:/Documentation/devicetree/binding/serial/fsl-lpuart.txt
Required properties:
- compatible :
- "fsl,vf610-lpuart" for lpuart compatible with the one integrated
on Vybrid vf610 SoC with 8-bit register organization
- reg : Address and length of the register set for the device
- interrupts : Should contain uart interrupt
- clocks : phandle + clock specifier pairs, one for each entry in clock-names
- clock-names : For vf610/ls1021a/imx7ulp, "ipg" clock is for uart bus/baud
clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used to access
lpuart controller registers, it also requires "baud" clock for module to
receive/transmit data.
Optional properties:
- dmas: A list of two dma specifiers, one for each entry in dma-names.
- dma-names: should contain "tx" and "rx".
- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
linux,rs485-enabled-at-boot-time: see rs485.txt
Note: Optional properties for DMA support. Write them both or both not.
Example:
uart0: serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
interrupts = <0 61 0x00>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
dmas = <&edma0 0 2>,
<&edma0 0 3>;
dma-names = "rx","tx";
};
LPUART1、2引脚RCW配置
RCW字段IIC3_PMUX,当该字段为3时引脚被用作LPUART1_SOUT、LPUART1_SIN
当RCW字段XSPI1_A_DATA74_PMUX为3时,引脚被用作LPUART2_SIN、LPUART2_SOUT功能
当RCW字段XSPI1_A_DATA30_PMUX为3时,引脚被用作LPUART3_SIN、LPUART3_SOUT功能
RCW配置
XSPI1_A_DATA30_PMUX=3
设备树节点注册
设备树路径:OK1028-linux-fs/packages/linux/linux/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
lpuart2: serial@2280000 {
+ compatible = "fsl,ls1028a-lpuart";
+ reg = <0x0 0x2280000 0x0 0x1000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ fsl,lpuart32;
+ status = "okay";
+ };
在复用LPUART3时需要在硬件上将QSPI_DISABLE引脚给硬件拉低,才能使用