寄存器类型

RW_REG

module RW_REG #(parameter DW=32,INIT=32'h0)
(
input						clk,
input						rst_n,
input						wen,
input		[DW-1:0]		datain,
input		[DW-1:0]		dataout
);

reg		[DW-1:0]			data;

always @(posedge clk or negedge rst_n) begin
	if(rst_n == 1'b0)
		data <= INIT;
	else if(wen == 1'b1)
		data <= datain;
end

assign dataout = data;

endmodule

RWU_REG

module RWU_REG #(parameter DW=32)
(
input						clk,
input						rst_n,
input						wen,
input		[DW-1:0]		datain,
input						updata,
input		[DW-1:0]		udata,

input		[DW-1:0]		dataout
);

reg		[DW-1:0]			data;

always @(posedge clk or negedge rst_n) begin
	if(rst_n == 1'b0)
		data <= {DW{1'b0}};
	else if(wen == 1'b1)
		data <= datain;
	else if(updata == 1'b1)
		data <= udata;
end

assign dataout = data;

endmodule

WIC_REG

module W1C_REG #(parameter DW=32)
(
input						clk,
input						rst_n,
input						wen,
input		[DW-1:0]		datain,
input		[DW-1:0]		ind,

input		[DW-1:0]		dataout
);

reg		[DW-1:0]			data;

always @(posedge clk or negedge rst_n) begin
	if(rst_n == 1'b0)
		data <= {DW{1'b0}};
	else if(wen == 1'b1)
		data <= (~datain & data) | ind;
	else if(updata == 1'b1)
		data <= data | ind;
end

assign dataout = data;

endmodule

W1PE_REG

module W1PE_REG #(parameter DW=32)
(
input						clk,
input						rst_n,
input						wen,
input		[DW-1:0]		datain,

input		[DW-1:0]		dataout
);

reg		[DW-1:0]			data;

always @(posedge clk or negedge rst_n) begin
	if(rst_n == 1'b0)
		data <= {DW{1'b0}};
	else 
		data <= datain & {DW{wen}};
end

assign dataout = data;

endmodule