verilog分频设计

最新推荐文章于 2023-01-09 10:13:59 发布

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最新推荐文章于 2023-01-09 10:13:59 发布

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分类专栏： verilog 文章标签： verilog fpga

本文链接：https://blog.csdn.net/qq_42125403/article/details/104677698

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任意倍数分频（verilog设计）

code

// Divide clock by 256

module clkdivder	
	(
		input wire clk,
		input wire reset,
		output reg clk_out
	);

reg [7:0] counter;

always @(posedge clk ) begin
	if (reset) begin
		counter <= 8'd0;
		clk_out <= 1'b0;
		
	end
	else if (counter == 8'h7f) begin
		counter <= 8'd0;
		clk_out <= ~clk_out;

	end
	else begin
		counter <= counter + 1;
	end
end
endmodule

任意N倍分频

module clkdivder	
	(
		input wire clk,
		input wire reset,
		output reg clk_out
	);

reg [7:0] counter;   //分频计数器
parameter N = number //number为待分频数
always @(posedge clk  ) begin
	if (reset) begin
		counter <= 8'd0;
		clk_out <= 1'b0;
		
	end
	else if (counter == N/2 -1) begin
		counter <= 8'd0;
		clk_out <= ~clk_out;

	end
	else begin
		counter <= counter + 1;
	end
end
endmodule