Verilog补码一位除法，加减交替法

module t(clk,in1,in2,out,WR,result);
input[7:0] in1;//输入1
input[7:0] in2;//输入2
output reg[7:0] out;//多余的可删
input clk;
input WR;//0读1算
reg flag;
reg[8:0] reg_A;
reg[8:0] reg_B;
reg[8:0] reg_Bfan;
reg[7:0] reg_C;
reg[4:0] i;
output reg[7:0] result;//结果
always@(posedge clk)
begin
	if(WR==0)
	begin
		reg_A={in1[7],in1[7:0]}; flag=1; reg_B={in2[7],in2[7:0]}; reg_Bfan=~reg_B+1; reg_C=0;
	end
	else if(flag==1)
	begin
		flag=0;
		if(reg_A[8]==reg_B[8])
				begin reg_A=reg_A+reg_Bfan; end 
		else
				begin reg_A=reg_A+reg_B;end
		
		for(i=1;i<=7;i=i+1)
		begin
			if(reg_A[8]==reg_B[8])
				begin reg_C[0]=1; reg_C={reg_C[6:0],1'b0}; reg_A={reg_A[7:0],1'b0}; reg_A=reg_A+reg_Bfan; end 
			else
				begin reg_C[0]=0; reg_C={reg_C[6:0],1'b0}; reg_A={reg_A[7:0],1'b0}; reg_A=reg_A+reg_B;end
		end
		reg_C[0]=1;
		result=reg_C;
	end
end
endmodule

如有不正确的地方，感谢指正