在上一篇使用verilog实现呼吸灯的博客中,里面的代码是结合我冬季学期公教中上发的硬件进行实现的,这里通过quartus13.1和modelsim联合仿真的形式进行验证。为了更好地进行展示和说明,部分代码进行了修改,主要是cnt_us上进行了更改,因为原先的板子系统时钟为24MHZ,这里在纯软件上实现改成了50MHZ。
呼吸灯实现代码
module sim_breath(
input clk,
output reg [2:0]led
);
// 寄存器
reg [9:0] cnt_s;
reg [9:0] cnt_ms;
reg [5:0] cnt_us;
reg a;
// 初始化
parameter T_s = 10'd999; // 1000
parameter T_ms = 10'd999; // 1000
parameter T_us = 6'd49; // 1us
initial
begin
a <= 1'b0;
led <= 3'b000;
cnt_s <= 10'd0;
cnt_ms <= 10'd0;
cnt_us <= 6'd0;
end
// 1us
always @ (posedge clk)
begin
if(cnt_us == T_us)
cnt_us <= 6'd0;
else
cnt_us <= cnt_us +6'd1;
end
// 1ms
always @ (posedge clk )
begin
if(cnt_us == T_us && cnt_ms == T_ms)
cnt_ms <= 10'd0;
else if(cnt_us == T_us)
cnt_ms <= cnt_ms + 10'd1;
end
// 1s
always @ (posedge clk)
begin
if(cnt_us == T_us && cnt_ms == T_ms && cnt_s == T_s)
cnt_s <= 10'd0;
else if(cnt_us == T_us && cnt_ms == T_ms)
cnt_s <= cnt_s + 10'd1;
end
// 标志位
always @ (posedge clk)
begin
if(cnt_us == T_us && cnt_ms == T_ms && cnt_s == T_s)
a <= ~a;
else
a <= a;
end
// 亮灯
always @ (posedge clk )
begin
if(cnt_s > cnt_ms && a ==1'b1)
led <= 3'b111;
else if(cnt_s < cnt_ms && a ==1'b1)
led <= 3'b000;
else if(cnt_s > cnt_ms && a ==1'b0)
led <= 3'b000;
else if(cnt_s < cnt_ms && a ==1'b0)
led <= 3'b111;
end
endmodule
编译
Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
仿真测试代码
注:为了方便观察,这里选用50MHZ的时钟
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// *****************************************************************************
// Generated on "05/08/2020 21:55:12"
// Verilog Test Bench template for design : sim_breath
//
// Simulation tool : ModelSim-Altera (Verilog)
//
`timescale 1 us/ 1 ns
module sim_breath_vlg_tst();
reg clk;
// wires
wire [2:0] led;
// assign statements (if any)
sim_breath i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.led(led)
);
initial
begin
clk <= 1'b0;
#40000 $stop;
end
always #10 clk <= ~clk;
endmodule
实验结果图
为了更好地演示呼吸的效果,这里把1s分成100份,每一份再分成100小份,再把每一小份分成50小份,进行仿真。
从图中可以看出占空比先逐渐增大再逐渐减小,说明此时先慢慢变暗之后再慢慢变亮,就像人的呼吸一样,缓缓吸气再缓缓吐气。