同步FIFO设计

同步FIFO设计

1. dual port 16X8 RAM 模块设计

   module dual_port (
       write_clk,
       read_clk,
       write_en,
       read_en,
       write_data,
       read_data,
       write_addr,
       read_data
       );
      
      parameter  RAM_WIDTH   = 8;
      parameter  RAM_DEPTH   =16;
      parameter  ADDR_WIDTH = 4;       // 2^4 =16

      input                        write_clk;
      input                        read_clk;
      input                        write_en;
      input                        read_en;
      input  [RAM_WIDTH-1:0]       write_data;
      input  [ADDR_WIDTH-1:0]      write_addr;
      input  [ADDR_WIDTH-1:0]      read_addr;
      output [RAM_WIDTH-1:0]       read_data;
      
      reg    [RAM_WIDTH-1:0]       read_data;

      reg    [RAM_WIDTH-1:0]  memory [RAM_DEPTH-1:0]   //memory是一个16x8的存储体
      
      always@(posedge write clk) begin   //写数据部分
         if (write_en)
             memory [write_addr]  <= write_data;   //时序逻辑，非阻塞赋值
      end
      
      always@(posedge read clk) begin  //读数据部分
         if (read_en)
             read_data <= memory [read_addr];
      end
 endmodule

2. 计数器Counter空满判断