FIFO深度计算

FIFO深度计算的关键在于： 在规定时间内传输的数据等于接收的数据，写快读慢的情况下，突发burst写入的数据减去该burst时间内读出的数据，多余的数据需要能缓冲下来，让接收端在剩下空闲的时间能从容地把多余的数据读出来。

下面看几道例题。

case1：

fA > fB with no idle cycles in both write and read.
Writing frequency = fA = 80MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
There are no idle cycles in both reading and writing which means that, all the items in the burst will be written and read in consecutive clock cycles.

计算方法（本题假设写数据和读数据位宽相同）：

总传输数据为120
把所有数据全部写入FIFO需要时间为120/80MHz=1500ns

该时间段（1500ns）内可以从FIFO中读出的数据为1500ns∗50MHz=75
多余的数据为120−75=45

所以FIFO的最小深度为45

case2

A > fB with one clk cycle delay between two successive reads and
writes.

这种情况和case1相同

case3

fA > fB with idle cycles in both write and read.
Writing frequency = fA = 80MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
No. of idle cycles between two successive writes is = 1.
No. of idle cycles between two successive reads is = 3.

计算方法

写时钟的等效频率为fW=fA/2=40MHz

读时钟的等效频率为fR=fB/4=12.5MHz
最小深度为120−120/fW∗fR=83

case4

fA > fB with duty cycles given for wr_enb and rd_enb.
Writing frequency = fA = 80MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
Duty cycle of wr_enb (write enable) = 50 % = ½.
Duty cycle of wr_enb (write enable) = 25 % = ¼.

和case3相同，只是问题描述方式不同

case5

fA < fB with no idle cycles in both write and read (i.e., the delay between two consecutive writes and reads is one clock cycle).
Writing frequency = fA = 30MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
There are no idle cycles in both reading and writing which means that, all the items in the burst will be written and read in consecutive clock cycles.

这种写慢读快的情况fifo的深度为1就够了。

case6

fA < fB with idle cycles in both write and read (duty cycles of wr_enb and rd_enb can also be given in these type of questions).
Writing frequency = fA = 30MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
No. of idle cycles between two successive writes is = 1.
No. of idle cycles between two successive reads is = 3.

这个case看似是写慢读快，但是因为有idle周期的存在导致

写时钟的等效频率为fW=fA/2=15MHz

读时钟的等效频率为fR=fB/4=12.5MHz
最小深度为120−120/fW∗fR=20

case7

fA = fB with no idle cycles in both write and read (i.e., the delay between two consecutive writes and reads is one clock cycle).
Writing frequency = fA = fB = 30MHz.
Burst Length = No. of data items to be transferred = 120.
There are no idle cycles in both reading and writing which means that, all the items in the burst will be written and read in consecutive clock cycles.

这种情况不需要fifo，如果clka和clkb有相位差，可以采用两级dff或者深度为1的fifo即可。

case8

fA = fB with idle cycles in both write and read (duty cycles of wr_enb and rd_enb can also be given in these type of questions).
Writing frequency = fA = 50MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
No. of idle cycles between two successive writes is = 1.
No. of idle cycles between two successive reads is = 3.

同样算等效时钟频率就行了。

case9

Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s)
Outgoing Data= 8 DATA/10 Clock.
Burst size = 160

可能有下面几种情况，以及每种情况下写完160个burst所需要的周期数

考虑最坏的情况case4，160个cycle就要写完160个数据的burst，在这160个时钟周期内能从fifo中读走 160/10∗8=128

个数据，所以fifo的深度为160-128=32

case10

Frequency (clk A) = frequency (clk B)/4
Period (en_B) = period (clk_A)*100
Duty cycle (en_B) = 25%

假设clkb=100MHz, 则clka=25MHz, 看起来是一个写慢读快的情况，不需要fifo。

但是因为第三个条件en_B的duty cycle只有1/4个周期，也就是在这个burst期间只有1/4的时间能从fifo中读出数据，这1/4周期的时间内是读快写慢，fifo不需要缓存数据。其余3/4个周期只有写，没有读，所以fifo的深度要能缓存下这3/4个周期中写入的数据。

从第二个条件可以看出burst的数据为100，总burst的时间为 100/25MHz=4000ns
, 3/4个周期就是3000ns，所以fifo的深度为
3000ns∗25MHz=75