HDLBits练习题practice——Latches and Flip-Flops

目录

Latches and Flip-Flops：

DFF+gate（Exams/m2014 q4d）

Mux and DFF(Mt2015 muxdff)

Mux and DFF（Exams/2014 q4a）

DFFs and gates（Exams/ece241 2014 q4）

Creat circuit from truth table（Exams/ece241 2013 q7)

Detect an edge（Edgedetect）

Edgedetect2

Edge capture register（Edgecapture）

Dual-edge triggered flip-flop（Dualedge）

---

说明：本篇文章仅作为个人学习。

Latches and Flip-Flops：

DFF+gate（Exams/m2014 q4d）

module top_module (
    input clk,
    input in, 
    output reg out);
    //进入了always块里面赋值就要定义为reg型
    
    always @(posedge clk)begin
       out <= in ^ out; 
    end

endmodule


/*另一种方法：在外面进行电路组合
module top_module (
    input clk,
    input in, 
    output out);
    
    wire d;
    
    assgin d = in ^ out; 
    
    always @(posedge clk)begin
       out <= d; 
    end

endmodule
*/

Mux and DFF(Mt2015 muxdff)

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q); //注意always中的output必须定义为reg型。
    
    wire d;
    
    assign d = L ? r_in : q_in;
    
    always @(posedge clk)begin
       Q <= d; 
    end

endmodule

Mux and DFF（Exams/2014 q4a）

module top_module (
    input clk,
    input w, R, E, L,
    output reg Q
);
    wire mux_1_out, D;
    
    assign mux_1_out = E ? w : Q;
    assign D = L ? R : mux_1_out;
    
    always @(posedge clk)begin
        Q <= D;
    end

endmodule



/*
module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
 
    always@(posedge clk)begin
        if(L)begin
            Q <= R;
        end
        else begin
            if(E)begin
                Q <= w;
            end
            else begin
                Q <= Q;
            end
        end
    end
endmodule
*/

这是一个带保持功能的D触发器

DFFs and gates（Exams/ece241 2014 q4）

//方法一
//使用模块完成，注意：此处给模块定义~q输出反而还会出错
module top_module (
    input clk,
    input x,
    output z
); 
    reg q_0;
    reg q_1;
    reg q_2;
    reg d_0, d_1, d_2;
    
    assign d_0 = x ^ q_0;
    assign d_1 = x & ~q_1;
    assign d_2 = x | ~q_2;
    
    
    ff DUT1 (.d(d_0),
              .clk(clk),
             .q(q_0));
    
    ff DUT2 (.d(d_1),
              .clk(clk),
             .q(q_1));
    
    ff DUT3 (.d(d_2),
              .clk(clk),
              .q(q_2));
    
    assign z = ~(q_0 | q_1 | q_2);
    
endmodule

module ff(
    input d,
    input clk,
    output reg q
);
    always @(posedge clk)begin
        q <= d;
    end
endmodule






//方法二
module top_module (
    input clk,
    input x,
    output z
); 
    reg q_1, q_2, q_3;
    
    always @(posedge clk)begin
        q_1 <= x ^ q_1;
        q_2 <= x & ~q_2;
        q_3 <= x | ~q_3;
    end
    
    assign z = ~(q_1 | q_2 | q_3);
    
endmodule



//方法三 直接定义q数组
module top_module (
    input clk,
    input x,
    output z
); 
    reg [2:0] q;
    
    always @(posedge clk)begin
        q[0] <= x ^ q[0];
        q[1] <= x & ~q[1];
        q[2] <= x | ~q[2];
    end
    
    assign z = ~|q;
    
endmodule

Creat circuit from truth table（Exams/ece241 2013 q7)

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    
    always@(posedge clk)begin
        case({j, k})
            2'b00:begin
                Q <= Q;
            end
            2'b01:begin
                Q <= 1'b0;
            end
            2'b10:begin
                Q <= 1'b1;
            end
            2'b11:begin
                Q <= ~Q;
            end
        endcase
    end

这是一个JK触发器。

Detect an edge（Edgedetect）

//方法一
module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] pedge
);
    reg [7:0] in_reg;
    
    always @(posedge clk)begin
        in_reg <= in;
    end
    
    always @(posedge clk)begin
        pedge <= in & ~in_reg;
    end

endmodule

//方法二

module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] pedge
);

    reg [7:0] in_reg;
    integer i;

    always@(posedge clk)begin
        for(i = 0; i <= 7; i = i + 1)begin
            if(in[i] & ~in_reg[i])begin
                pedge[i] = 1'b1;
            end
            else begin
                pedge[i] = 1'b0;
            end
        end
    end
    */
 

Edgedetect2

module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] anyedge
);
    reg [7:0] in_reg;
    
    always @(posedge clk)begin
        in_reg <= in;
    end
    
    
    always @(posedge clk)begin 
        anyedge <= in ^ in_reg;        
    end

endmodule

双边沿检测器

Edge capture register（Edgecapture）

//下降沿检测，如果位检测到一次下降沿，则位输出一直保持高电平
//直到reset信号置零。
module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    reg [31:0] in_reg;
    
    always @(posedge clk)begin
        in_reg[31:0] <= in[31:0];
    end
    
    always @(posedge clk)begin
        if(reset == 1)begin
            out <= 0;
        end
        else begin
        	out <= ~in & in_reg | out;	//in是最新的信号，in_reg为上个周期的信号
        end
    end

endmodule

Dual-edge triggered flip-flop（Dualedge）

//
module top_module (
    input clk,
    input d,
    output q
);
    reg q_d1;
    reg q_d2;
    
    always@(posedge clk)begin
        q_d1 <= d ^ q_d2;
    end
    always@(negedge clk)begin
        q_d2 <= d ^ q_d1;
    end
    
    assign q = q_d1 ^ q_d2;
    
endmodule