HDLbits 刷题答案practice——Circuits_More circuits

目录

3.2.4.1 Rule 90（Rule90）

3.2.4.2 Rule 110（Rule110）

3.2.4.3 Conway's Game of Life 16x16（Conwaylife）

---

3.2.4.1 Rule 90（Rule90）

//一维cellular automaton设计
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    
    always @(posedge clk)begin
        if(load)begin
           q <= data; 
        end
        else begin
            q <= {1'b0,q[511:1]} ^ {q[510:0], 1'b0};//移位按位异或
        end
    end

endmodule

此题目就是一个自动细胞机的一个设计，cellular automaton具体概念可以参考Cellular automaton。

3.2.4.2 Rule 110（Rule110）

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output reg [511:0] q
); 

    always @(posedge clk)begin
        if(load)begin
            q <= data;
        end
        else begin
            q <= (q ^ {q[510:0], 1'b0}) | (~{1'b0, q[511:1]} & {q[510:0], 1'b0});//Q=B⊕C+~AC
        end
    end
endmodule

3.2.4.3 Conway's Game of Life 16x16（Conwaylife）

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q ); 
    
    wire [323:0] ex_q; //扩展成18*18的矩阵
    wire [255:0] q_next;
    reg [3:0] flag;
    integer i, j;
    
    //逐行进行连线操作（wire型操作可以同时改变原来q的值）
    assign	ex_q[17:0] 			= 	{q[240]	,	q[255:240]	,q[255]	};
    assign	ex_q[35:18] 		= 	{q[0]	,	q[15:0]    	,q[15]	};
    assign	ex_q[53:36] 		= 	{q[16]	,  	q[31:16]   	,q[31]	};
    assign	ex_q[71:54] 		= 	{q[32]	,  	q[47:32]   	,q[47]	};
    assign	ex_q[89:72] 		= 	{q[48]	,  	q[63:48]   	,q[63]	};
    assign	ex_q[107:90] 		= 	{q[64]	,  	q[79:64]   	,q[79]	}; 
    assign	ex_q[125:108] 		= 	{q[80]	,  	q[95:80]   	,q[95]	};
    assign	ex_q[143:126] 		= 	{q[96]	,  	q[111:96]  	,q[111]	};
    assign	ex_q[161:144] 		= 	{q[112]	, 	q[127:112] 	,q[127]	};
    assign	ex_q[179:162] 		= 	{q[128]	, 	q[143:128] 	,q[143]	};
    assign	ex_q[197:180] 		= 	{q[144]	,	q[159:144]	,q[159]	};
    assign	ex_q[215:198] 		= 	{q[160]	,	q[175:160]	,q[175]	};
    assign	ex_q[233:216] 		= 	{q[176]	,	q[191:176]	,q[191]	};
    assign	ex_q[251:234] 		= 	{q[192]	,	q[207:192]	,q[207]	};
    assign	ex_q[269:252] 		= 	{q[208]	,	q[223:208]	,q[223]	};
    assign	ex_q[287:270] 		= 	{q[224]	,	q[239:224]	,q[239]	}; 
    assign	ex_q[305:288] 		= 	{q[240]	,	q[255:240]	,q[255]	};
    assign	ex_q[323:306] 		= 	{q[0]	,	q[15:0]		,q[15]	};


    //判断操作
    always@(*)begin
        for(i=0;i<16;i=i+1)begin
            for(j=0;j<16;j=j+1)begin
                flag = ex_q[i*18+j] + ex_q[i*18+j+1] + ex_q[i*18+j+2] +
                ex_q[(i+1)*18+j] + ex_q[(i+1)*18+j+2] 
                + ex_q[(i+2)*18+j] + ex_q[(i+2)*18+j+1] + ex_q[(i+2)*18+j+2];
                if(flag <= 1 | flag >= 4)begin
                    q_next[i*16+j] = 1'b0;
                end
                else if(flag == 3)begin
                    q_next[i*16+j] = 1'b1;
                end
                else begin
                    q_next[i*16+j] =  q[i*16+j];
                end
            end
        end
    end
    

    always@(posedge clk)begin
        if(load)begin
           q <= data; 
        end
        else begin
           q <= q_next;
        end
    end
endmodule