简易计时器verilog代码实现及仿真
简易计时器verilog代码实现及仿真
本文章讲解简易计时器的功能与代码实现。
主要功能
实现在设定值范围内的计时,并在计时结束时保持最大值。
1.timer.v
module timer(clk,rst,time_min,time_sec,start,minute,second,time_up);
input clk,rst;
input [2:0]time_min;
input [5:0]time_sec;
input start;
output reg [2:0]minute;
output reg [5:0]second;
output reg time_up;
always@(posedge clk)
begin
if(!rst)
begin
minute=0;
second=0;
time_up=0;
end
else
begin
if(start&&rst)
begin
if(minute<time_min)
begin
if(second<6'd59)
second<=second+6'd1;
else
begin
second<=0;
minute<=minute+3'd1;
//注意此处要完成59-0的转换,必须进行阻塞赋值
end
end
if(minute==time_min)
begin
if(second<time_sec)
begin
second=second+6'd1;
end
if(second==time_sec)
begin
time_up=1;
end
end
if(!rst)
begin
minute=0;
second=0;
end
end
end
end
endmodule
testbench.v
`timescale 1ns/1ns
module test_tb();
reg clk;
reg rst;
reg [2:0]time_min;
reg [5:0]time_sec;
reg start;
wire [2:0]minute;
wire [5:0]second;
wire time_up;
timer t(.clk(clk),.rst(rst),.time_min(time_min),.time_sec(time_sec),.start(start),.minute(minute),.second(second),.time_up(time_up));
initial
begin
clk=0;
rst=0;
time_min=3'd3;
time_sec=6'd48;
start=0;
#100;
rst=1;
#200;
start=1;
#9500;
rst=0;
#500;
$stop;
end
always #20 clk=~clk;
endmodule
仿真结果