可以参考的管脚配置 https://wenku.baidu.com/view/a94fc49cbe1e650e53ea992f.html
实验一 五输入表决器设计
程序设计
module first(a,b,c,d,e,f);
input a,b,c,d,e;
output f;
wire a,b,c,d,e,f;
assign f=(a&b&c)|(a&b&d)|(a&b&e)|(a&c&d)|(a&c&e)|(a&d&e)|(b&c&d)|(b&c&e)|(b&d&e)|(c&d&e);
endmodule
测试代码
module test;
// Inputs
reg a;
reg b;
reg c;
reg d;
reg e;
// Outputs
wire f;
// Instantiate the Unit Under Test (UUT)
first uut (
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f)
);
initial begin
// Initialize Inputs
a = 0;b = 0;c = 0;d = 0;e = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a = 1;b = 1;c = 1;d = 1;e = 0;
#100;
a = 0;b = 1;c = 1;d = 0;e = 1;
#100;
a = 0;b = 0;c = 0;d = 1;e = 1;
end
endmodule
实验二 多路数据选择器设计
程序设计
module second(a,b,c,d,y,sel,en);
input [1:0]a;
input [1:0]b;
input [1:0]c;
input [1:0]d;
input [1:0]sel;
input en;
output [1:0]y;
reg [1:0]y;
always@(a or b or c or d or sel or en)
if(en) y<=0;
else case(sel)
0: y<=a;
1: y<=b;
2: y<=c;
3: y<=d;
endcase
endmodule
测试代码
module test2;
// Inputs
reg [1:0] a;
reg [1:0] b;
reg [1:0] c;
reg [1:0] d;
reg [1:0] sel;
reg en;
// Outputs
wire [1:0] y;
// Instantiate the Unit Under Test (UUT)
second uut (
.a(a),
.b(b),
.c(c),
.d(d),
.y(y),
.sel(sel),
.en(en)
);
initial begin
// Initialize Inputs
a[0]=1;a[1]=1;
b[0]=0;b[1]=0;
c[0]=0;c[1]=0;
d[0]=0;d[1]=0;
en = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a[0]=1;a[1]=1;
b[0]=0;b[1]=0;
c[0]=0;c[1]=0;
d[0]=0;d[1]=0;
sel[0]=0;sel[1]=0;
en = 0;
#100;
a[0]=1;a[1]=1;
b[0]=1;b[1]=0;
c[0]=0;c[1]=0;
d[0]=0;d[1]=0;
sel[0]=1;sel[1]=0;
en = 0;
#100;
a[0]=1;a[1]=1;
b[0]=0;b[1]=0;
c[0]=0;c[1]=1;
d[0]=0;d[1]=0;
sel[0]=0;sel[1]=1;
en = 0;
#100;
a[0]=1;a[1]=1;
b[0]=0;b[1]=0;
c[0]=0;c[1]=0;
d[0]=1;d[1]=1;
sel[0]=1;sel[1]=1;
en = 0;
end
endmodule
实验三 译码器设计
程序设计
module sm(data_out,G,GA,GB,a,b,c);
input G,GA,GB;
wire G,GA,GB;
input a,b,c;
wire a,b,c;
reg [2:0] ans;
output[7:0] data_out;
reg[7:0] data_out;
always @ (a or b or c)
begin
ans[0]=a;ans[1]=b;ans[2]=c;
end
always@(ans or G or GA or GB)
begin
case(ans)
3'd0:data_out = 8'b11111110;
3'd1:data_out = 8'b11111101;
3'd2:data_out = 8'b11111011;
3'd3:data_out = 8'b11110111;
3'd4:data_out = 8'b11101111;
3'd5:data_out = 8'b11011111;
3'd6:data_out = 8'b10111111;
3'd7:data_out = 8'b01111111;
endcase
if(!G) data_out = 8'b11111111;
if(GA) data_out = 8'b11111111;
if(GB) data_out = 8'b11111111;
end
endmodule
测试代码
module smm;
// Inputs
reg G;
reg GA;
reg GB;
reg a;
reg b;
reg c;
// Outputs
wire [7:0] data_out;
// Instantiate the Unit Under Test (UUT)
sm uut (
.data_out(data_out),
.G(G),
.GA(GA),
.GB(GB),
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
G = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
GA=1;
#100
GB=1;
#100
G=1;GA=0;GB=0;
c=0;b=0;a=0;
#100
G=1;GA=0;GB=0;
c=0;b=0;a=1;
#100
G=1;GA=0;GB=0;
c=0;b=1;a=0;
#100
G=1;GA=0;GB=0;
c=0;b=1;a=1;
#100
G=1;GA=0;GB=0;
c=1;b=0;a=0;
#100
G=1;GA=0;GB=0;
c=1;b=0;a=1;
#100
G=1;GA=0;GB=0;
c=1;b=1;a=0;
#100
G=1;GA=0;GB=0;
c=1;b=1;a=1;
end
endmodule
实验四 二进制优先级编码器
程序设计
module qwq(en,p,f,down);
input en;
wire en;
input [7:0]p;
wire [7:0]p;
output down;
integer down;
output [2:0]f;
reg [2:0]f;
always @ (en or p or down)
begin
if(en) down=1;
else down=0;
if(p[7]) f=3'b111;
else if(p[6]) f=3'b110;
else if(p[5]) f=3'b101;
else if(p[4]) f=3'b100;
else if(p[3]) f=3'b011;
else if(p[2]) f=3'b010;
else if(p[1]) f=3'b001;
else if(p[0]) f=3'b000;
else down=0;
if(!down) f=3'b000;
end
endmodule
测试代码
module qaq;
// Inputs
reg en;
reg [7:0] p;
// Outputs
wire [2:0] f;
wire down;
// Instantiate the Unit Under Test (UUT)
qwq uut (
.en(en),
.p(p),
.f(f),
.down(down)
);
initial begin
// Initialize Inputs
en = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
en=0;
p=8'b00000000;
#100
en=1;
p=8'b10000000;
#100
en=1;
p=8'b01000000;
#100
en=1;
p=8'b00100000;
#100
en=1;
p=8'b00010000;
#100
en=1;
p=8'b00001000;
#100
en=1;
p=8'b00000100;
#100
en=1;
p=8'b00000010;
#100
en=1;
p=8'b00000001;
end
endmodule
实验五 数值比较器设计
程序设计
module third( Y ,A ,B );
input [3:0] A ;
wire [3:0] A ;
input [3:0] B ;
wire [3:0] B ;
output [2:0] Y ;
reg [2:0] Y ;
always @ ( A or B )
begin
if ( A > B )
Y <= 3'b011;
else if ( A == B)
Y <= 3'b101;
else
Y <= 3'b110;
end
endmodule
测试代码
module test3;
// Inputs
reg [3:0] A;
reg [3:0] B;
// Outputs
wire [2:0] Y;
// Instantiate the Unit Under Test (UUT)
third uut (
.Y(Y),
.A(A),
.B(B)
);
initial begin
// Initialize Inputs
A=4'b1011;B=4'b1011;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A=4'b1111;B=4'b1011;
#100;
A=4'b0101;B=4'b1010;
end
endmodule
实验六 加法器设计
程序设计
module a(a,b,c1,c2,sum);
input [3:0] a;
input [3:0] b;
input c1;
output c2;
output [3:0] sum;
assign {c2,sum}=a+b+c1;
endmodule
测试代码
module a_s;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg c1;
// Outputs
wire c2;
wire [3:0] sum;
// Instantiate the Unit Under Test (UUT)
a uut (
.a(a),
.b(b),
.c1(c1),
.c2(c2),
.sum(sum)
);
initial begin
// Initialize Inputs
a<=4'd0;b<=4'd0;c1=1'b0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a<=4'd0;b<=4'd1;c1=1'b0;
#100;
a<=4'd0;b<=4'd2;c1=1'b0;
#100;
a<=4'd0;b<=4'd3;c1=1'b0;
#100;
a<=4'd0;b<=4'd4;c1=1'b0;
#100;
a<=4'd1;b<=4'd0;c1=1'b1;
#100;
a<=4'd2;b<=4'd0;c1=1'b0;
#100;
a<=4'd4;b<=4'd0;c1=1'b1;
#100;
a<=4'd4;b<=4'd3;c1=1'b1;
#100;
a<=4'd7;b<=4'd8;c1=1'b1;
end
endmodule
实验七
程序设计
module a(a,b,c1,c2,ans,f,zf,cf);
input [3:0] a;
input [3:0] b;
input c1;
input f;
output c2;
output [3:0] ans;
output cf;
output zf;
assign {c2,ans}=f?(a-b-c1):(a+b+c1);
assign zf=ans?0:1;
assign cf=f?(!c2):(c2);
endmodule
测试代码
module a_t;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg c1;
reg f;
// Outputs
wire c2;
wire [3:0] ans;
wire zf;
wire cf;
// Instantiate the Unit Under Test (UUT)
a uut (
.a(a),
.b(b),
.c1(c1),
.c2(c2),
.ans(ans),
.f(f),
.zf(zf),
.cf(cf)
);
initial begin
// Initialize Inputs
a=4'd1;b=4'd2;c1=0;f=1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a=4'd8;b=4'd7;c1=1;f=0;
#100;
a=4'd4;b=4'd3;c1=0;f=1;
#100;
a=4'd2;b=4'd4;c1=1;f=0;
#100;
a=4'd5;b=4'd5;c1=1;f=1;
#100;
a=4'd6;b=4'd7;c1=0;f=0;
#100;
a=4'd0;b=4'd1;c1=1;f=0;
#100;
a=4'd4;b=4'd4;c1=0;f=0;
end
endmodule