Verilog HDL 程序设计（一）

1、4位全加器

module adder_4(a,b,cin,sum,cout);
	
	input [3:0]a,b;
	input cin;
	output [3:0]sum;
	output cout;
	
	assign {cout,sum}=a+b+cin;

endmodule 

`timescale 1ns/1ns
module adder_4_tb;
	reg [3:0]a;
	reg [3:0]b;
	reg cin;
	
	wire [3:0]sum;
	wire cout;
	integer i,j;

	adder_4  adder_4(
	.a(a),
	.b(b),
	.cin(cin),
	.sum(sum),
	.cout(cout));
	

	
	always #5 cin = ~cin;
	
	initial 
	begin 
		a=0;b=0;cin=0;
		for(i=1;i<16;i=i+1)
		begin 
			#10;a=i;
			for(j=1;j<16;j=j+1)
			begin 				
			#10;b=j;
			end
			end  
		#160;
		$stop;
	end

	
endmodule

 2、4位计数器

module count_4(clk,Rst_n,out);
	
	input clk;
	input Rst_n;
	output reg [3:0]out;
	
	always @(posedge clk or negedge Rst_n)
	begin
		if(!Rst_n)
			out <= 4'b0;
		else 
			out <= out + 1'b1;
	end
endmodule

`timescale 1ns/1ns
module count_4_tb;

	reg clk;
	reg Rst_n;
	wire [3:0]out;
	
	count_4 count_40(
	.clk(clk),
	.Rst_n(Rst_n),
	.out(out));
	
	initial clk=1;
	always #10 clk=~clk;
	
	initial 
	begin 
		Rst_n=0;
		#20;
		Rst_n=1;
		#200;
		$stop;
	end
	
	
endmodule