D触发器-verilog

//D触发器
module dff(
	input clk,
	input rst_n,
	input d,
	output reg q
);

always @ (posedge clk or negedge rst_n)
begin
	if(!rst_n)
		q < = 0;
	else
		q <= d;
end

endmudule

//仿真代码
module sim_dff();
reg clk;
reg rst_n;
reg d;
wire q;

dff u1(
	.clk (clk),
	.rst_n (rst_n),
	.d (d),
	.q (q),
);

initial begin
	clk = 0;
	rst_n = 1;
	d = 0;
	#20;
	d = 1;
end

always #10 clk = ~clk;

endmodule