fpga学习——序列检测器11101

1.状态转移图

2.代码

//11101
module ex_check(
     input  wire  clk,
	 input  wire  rst,
	 input  wire  A,
	 output  reg  k
);

parameter  s1=6'b000_001;
parameter  s2=6'b000_010;
parameter  s3=6'b000_100;
parameter  s4=6'b001_000;
parameter  s5=6'b010_000;
parameter  s6=6'b100_000;

reg  [5:0]  state;

always @ (posedge clk or negedge rst)
     if(rst == 1'b0)
	   state <= s1;
	 else
	   case (state)
	     s1: if(A==1'b1)
		      state <= s2;
		     else 
              state <= s1;
         s2: if(A==1'b1)
		      state <= s3;
		     else 
              state <= s1;
         s3: if(A==1'b1)
		      state <= s4;
		     else 
              state <= s1;
         s4: if(A==1'b0)
		      state <= s5;
		     else 
              state <= s4;
         s5: if(A==1'b1)
		      state <= s6;
		     else 
              state <= s1;
         s6: state <= s1;
		 default: state <= s1;
       endcase			  

always @ (posedge clk or negedge rst)
     if(rst == 1'b0)
	   k <= 1'b0;
	 else if(state == s5 && A ==1'b1)
	   k <= 1'b1;
	 else
	   k <= 1'b0;

endmodule

3.测试代码

`timescale 1ns/1ns

module tb_ex_check;

reg  clk,rst;
reg  A;
wire  k;

initial  begin
  clk = 0;
  rst = 0;
  #100;
  rst = 1;
end

initial  begin
  rand_bit();
end

always  #10  clk <= ~clk;

ex_check  ex_check_inst(
  .clk(clk),
  .rst(rst),
  .A(A),
  .k(k)
);

task  rand_bit();
  integer  i;
  begin
    for(i=0;i<255;i=i+1)
	  begin
	    @(posedge clk)
		  A <= {$random} % 2;  //产生0、1的随机数，$random % 2是产生-2到1的随机数
	  end
  end
endtask

endmodule

4.自动化仿真文件

quit -sim
.main clear

vlib ./lib
vlib ./lib/work_a/
vlib ./lib/design
vmap base_space ./lib/work_a/
vmap design ./lib/design/

vlog -work base_space ./tb_ex_check.v
vlog -work ./../design/*.vlib

#-t 运行仿真的时间精度是ns
#-L 是链接库关键字
vsim -t ns -voptargs=+acc -L base_space -L design base_space.tb_ex_check

#创建虚拟信号，枚举
virtual  type  {
{01  s1}
{02  s2}
{04  s3}
{08  s4}
{10  s5}
{20  s6}
}  vir_new_singal

add wave -divider {tb_ex_check}
add wave tb_ex_check/*
add wave -divider {ex_check}
#顶层/例化的名字，/*中*是通配符，匹配所有信号
add wave tb_ex_check/ex_check_inst/*

#创建一个vir_new_singal类型的信号，也就是把state进行类型转换
virtual  function  {(vir_new_singal)tb_ex_check/ex_check_inst/state}  new_state
add  wave  -color  red  tb_ex_check/ex_check_inst/new_state

run 1us

5.仿真结果