VHDL语言设计乐曲演奏电路
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FPGA乐曲演奏电路设计之music1
-- megafunction wizard: %ROM: 1-PORT%-- GENERATION: STANDARD-- VERSION: WM1.0-- MODULE: altsyncram -- ============================================================-- File Name: music1.vhd-- Megafunction Name(s):-- altsyncram---- Simulation Libr原创 2020-12-13 08:47:42 · 720 阅读 · 0 评论 -
pll1
-- megafunction wizard: %ALTPLL%-- GENERATION: STANDARD-- VERSION: WM1.0-- MODULE: altpll -- ============================================================-- File Name: pll1.vhd-- Megafunction Name(s):-- altpll---- Simulation Library Files(s):-原创 2020-12-12 19:27:50 · 425 阅读 · 0 评论 -
F_CODE解码器VHDL程序
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F_CODE IS PORT(INX: IN STD_LOGIC_VECTOR (0 TO 3); CODE: OUT STD_LOGIC_VECTOR(0 TO 3); H:OUT STD_LOGIC; TO1:OUT STD_LOGIC_VECTOR(0 TO 10));END;ARCHITECTURE one OF F_CODE ISBEGIN原创 2020-12-12 19:24:09 · 656 阅读 · 1 评论 -
乐曲演奏顶层文件
一共要设计这九个模块,并将这几个模块例化为元件,并用信号线连接起来就行了,重点是要理解并看懂原理图u1: pll1 PORT MAP(inclk0=>CLK_20,c0=>net1);u2:CNT10T PORT MAP( CO1=>net1,Q=>net2);u3:CNT2_18T PORT MAP(CO2=>net2,Q=>net3);u4:CNT138T PORT MAP(CLK=>net3,Q=>net4);u5:music1 PORT MA原创 2020-12-12 18:04:19 · 292 阅读 · 0 评论 -
CNT10T
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10T ISPORT(CO1:IN STD_LOGIC;Q:OUT STD_LOGIC);END CNT10T;ARCHITECTURE bhv OF CNT10T ISSIGNAL Q1:STD_LOGIC_VECTOR(0 TO 3);BEGINPROCESS(CO1) BEGINIF CO1’EVENT AND C原创 2020-12-12 18:43:38 · 249 阅读 · 0 评论 -
CNT2_18T
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT2_18T IS PORT(CO2:IN STD_LOGIC; Q:OUT STD_LOGIC);END CNT2_18T;ARCHITECTURE bhv OF CNT2_18T IS SIGNAL Q1:STD_LOGIC_VECTOR(0 TO 17); BEGIN PROCESS(CO2) BEGIN原创 2020-12-12 18:06:32 · 175 阅读 · 0 评论 -
CNT138T
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT138T ISPORT(CLK:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(0 to 7));END CNT138T;ARCHITECTURE bhv OF CNT138T ISSIGNAL Q1:STD_LOGIC_VECTOR(0 TO 7);BEGINPROCESS(CLK) BEGIN原创 2020-12-12 18:44:52 · 152 阅读 · 1 评论 -
Decl7s
Library Ieee;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Decl7s ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);LED7s:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));END;ARCHITECTURE one OF Decl7s ISBEGINPROCESS(A)BEGINCASE A ISWHEN “0000” => LED7s <=“0111111”;WHEN “原创 2020-12-12 18:46:34 · 489 阅读 · 0 评论 -
CNT2T
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT2T ISPORT(CO3:IN STD_LOGIC;Q:OUT STD_LOGIC);END CNT2T;ARCHITECTURE bhv OF CNT2T ISSIGNAL Q1:STD_LOGIC_VECTOR(0 TO 1);BEGINPROCESS(CO3) BEGINIF CO3’EVENT AND CO3=原创 2020-12-12 18:42:20 · 218 阅读 · 0 评论 -
数控分频模块
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY spker IS PORT(clk:IN STD_LOGIC; Tn:IN STD_LOGIC_VECTOR(0 TO 10); SpkS:OUT STD_LOGIC);END spker;ARCHITECTURE behav OF spker IS SIGNAL Q:STD_LOGIC_VECTOR(0原创 2020-12-12 17:59:25 · 162 阅读 · 0 评论