【Verilog】模16可逆流水灯

功能：

实现模16的可逆流水灯

 

Verilog代码：

`timescale 1ns / 1ps

module Liushuideng_16(en, clk, y);
	input clk, en;
	output[15:0] y;
	reg[15:0] y;
	reg[3:0] m;
	reg i, flag1, flag2;
	reg[15:0] j;
	reg[8:0] k;
	
	initial
		begin
			i = 0;
			m = 0;
			y = 0;
			j = 0;
			k = 0;
			flag1 = 0;
			flag2 = 0;
		end
	
	//100M100000分频得到1KHZ
	always@(posedge clk)
		begin
			if(j == 16'd49999)
				begin
					flag1 <= ~flag1;
					j <= 0;
				end
			else j <= j + 1;
		end
	
	//1KHZ千分频得到1HZ
	always@(posedge flag1)
		begin
			if(k == 9'd499)
				begin
					flag2 <= ~flag2;
					k <= 0;
				end
			else k <= k + 1;
		end
	
	//模16可逆计数器
	always@(posedge flag2)
		begin
			if(m==4'b1111) i = 1;
			if(m==4'b0000) i = 0;
			
			if(en==0) m <= m;
			else if(i==0) m <= m + 1'b1;
			else m <= m - 1'b1;
		end

	//4—16译码器
	always@(m) begin
		if(en==0) y = 0;
		else
			case({en, m})
				5'b10000: y = 16'b0000_0000_0000_0001;
				5'b10001: y = 16'b0000_0000_0000_0010;
				5'b10010: y = 16'b0000_0000_0000_0100;
				5'b10011: y = 16'b0000_0000_0000_1000;
				5'b10100: y = 16'b0000_0000_0001_0000;
				5'b10101: y = 16'b0000_0000_0010_0000;
				5'b10110: y = 16'b0000_0000_0100_0000;
				5'b10111: y = 16'b0000_0000_1000_0000;
				5'b11000: y = 16'b0000_0001_0000_0000;
				5'b11001: y = 16'b0000_0010_0000_0000;
				5'b11010: y = 16'b0000_0100_0000_0000;
				5'b11011: y = 16'b0000_1000_0000_0000;
				5'b11100: y = 16'b0001_0000_0000_0000;
				5'b11101: y = 16'b0010_0000_0000_0000;
				5'b11110: y = 16'b0100_0000_0000_0000;
				5'b11111: y = 16'b1000_0000_0000_0000;
			endcase
	end
endmodule 

 

测试代码：

`timescale 1ns / 1ps

module test;
	reg en;
	reg clk;
	wire [15:0] y;
	
	Liushuideng_16 uut (
		.en(en), 
		.clk(clk), 
		.y(y)
	);

	initial begin
		en = 1;
		clk = 0;
	end
	
	always #5 clk = ~clk;
      
endmodule