实验一 实验环境搭建与数字电路正向设计方法

实验一 实验环境搭建与数字电路正向设计方法

图	电路功能
Figure 2.72	二选一结合1位半加器
Figure2.40	二选一多路选择器
Figure2.42	二选一多路选择器
Figure2.45	1位半加器

Figure 2.72 电路

shared.v

module shared(a,b,c,d,m,s1,s0);
	input a,b,c,d,m;
	output s1,s0;
	wire w1,w2;
	mux2to1 U1(a,c,m,w1);
	mux2to1 U2(b,d,m,w2);
	adder U3(w1,w2,s1,s0);
endmodule

module mux2to1(x1,x2,s,f);
	input x1,x2,s;
	output f;
	assign f=(~s&x1)|(s&x2);
endmodule

module adder(a,b,s1,s0);
	input a,b;
	output s1,s0;
	assign s1 = a & b;
	assign s0 = a ^ b;
endmodule

testbench

`timescale 1ns/1ps
module tb_shared;
reg a_test;
reg b_test;
reg c_test;
reg d_test;
reg m_test;
wire s1_test;
wire s0_test;

initial
m_test = 0;

always #40 m_test = ~m_test;

initial
begin
a_test = 0;
b_test = 0;
c_test = 0;
d_test = 0;

#20
a_test = 0;
b_test = 1;
c_test = 0;
d_test = 1;

#40
a_test = 1;
b_test = 1;
c_test = 1;
d_test = 1;

#80
a_test = 1;
b_test = 0;
c_test = 1;
d_test = 0;
end

shared UUT_shared(.a(a_test),.b(b_test),.c(c_test),.d(d_test),.m(m_test),.s1(s1_test),.s0(s0_test));
endmodule

Figure 2.40电路

example3.v

module example3(x1,x2,s,f);
	input x1,x2,s;
	output f;

	assign f=(~s & x1) | (s & x2);

endmodule

testbench

`timescale 1ns/1ps
module tb_example3;
reg x1;
reg x2;
reg s;
wire f;

initial
begin
x1 = 0;
x2 = 0;
s = 0;

#20
x1 = 0;
x2 = 0;
s = 1;

#20
x1 = 0;
x2 = 1;
s = 0;

#20
x1 = 0;
x2 = 1;
s = 1;

#20
x1 = 1;
x2 = 0;
s = 0;

#20
x1 = 1;
x2 = 0;
s = 1;

#20
x1 = 1;
x2 = 1;
s = 0;

#20
x1 = 1;
x2 = 1;
s = 1;

#20
x1 = 1;
x2 = 1;
s = 1;
end

example3 example(.x1(x1),.x2(x2),.s(s),.f(f));
endmodule

Figure 2.42电路

example5.v

module example3(x1,x2,s,f);
	input x1,x2,s;
	output f;

	assign f=(~s & x1) | (s & x2);

endmodule

testbench

`timescale 1ns/1ps
module tb_example5;
reg x1;
reg x2;
reg s;
wire f;

initial
begin
x1 = 0;
x2 = 0;
s = 0;

#20
x1 = 0;
x2 = 0;
s = 1;

#20
x1 = 0;
x2 = 1;
s = 0;

#20
x1 = 0;
x2 = 1;
s = 1;

#20
x1 = 1;
x2 = 0;
s = 0;

#20
x1 = 1;
x2 = 0;
s = 1;

#20
x1 = 1;
x2 = 1;
s = 0;

#20
x1 = 1;
x2 = 1;
s = 1;

#20
x1 = 1;
x2 = 1;
s = 1;
end

example5 example(.x1(x1),.x2(x2),.s(s),.f(f));
endmodule

Figure 2.45

adder.v

module adder(a,b,s1,s0);
	input a,b;
	output s1,s0;

assign s1 = a & b;
assign s0 = a ^ b;

endmodule

testbench

`timescale 1ns/1ps
module tb_adder;
reg a;
reg b;
wire s0;
wire s1;

initial
begin
a = 0;
b = 0;

#20
a = 0;
b = 1;

#20
a = 1;
b = 0;

#20
a = 1;
b = 1;

#20
a = 1;
b = 1;
end

adder adder(.a(a),.b(b),.s0(s0),.s1(s1));

endmodule