实验背景:通过指令系统表我们可以设计一个由指令码映射到指令信号的译码器。其中指令码为 8 位二进制码,译码器的输出端为指令操作。
VHDL代码
library ieee;
use ieee.std_logic_1164.all;
entity moxingji is
port(a: in std_logic_vector(7 downto 0);
en:in std_logic;
MOVA,MOVB,MOVC,ADD,SUB,OR0,NOT0,RSR,RSL,JMP,JZ,JC,IN0,OUT0,NOP,HALT: out std_logic);
end moxingji;
architecture aaa of moxingji is
signal x: std_logic_vector(0 to 7);
signal R1,R2: std_logic;
begin
x<=not a;
R1<=not(a(0)and a(1)and a(2)and a(3)and a(4)and a(5)and en);
R2<=not(a(0)and a(1)and a(2)and a(3)and a(6)and a(7)and en);
MOVA<=a(0)and a(1)and a(2)and a(3)and R1 and R2 and en; --1111xxxx-111111xx-1111xx11
MOVB<=a(0)and a(1)and a(2)and a(3)and a(4)and a(5)and en; --111111xx
MOVC<=a(0)and a(1)and a(2)and a(3)and a(6)and a(7)and en; --1111xx11
ADD<=a(0)and x(1)and x(2)and a(3)and en; --1001
SUB<=x(0)and a(1)and a(2)and x(3)and en; --0110
OR0<=a(0)and x(1)and a(2)and a(3)and en; --1011
NOT0<=x(0)and a(1)and x(2)and a(3)and en; --0101
RSR<=a(0)and x(1)and a(2)and x(3)and x(6)and x(7)and en; --101000
RSL<=a(0)and x(1)and a(2)and x(3)and a(6)and a(7)and en; --101011
JMP<=x(0)and x(1)and a(2)and a(3)and x(4)and x(5)and x(6)and x(7)and en; --00110000
JZ<=x(0)and x(1)and a(2)and a(3)and x(4)and x(5)and x(6)and a(7)and en; --00110001
JC<=x(0)and x(1)and a(2)and a(3)and x(4)and x(5)and a(6)and x(7)and en; --00110010
IN0<=x(0)and x(1)and a(2)and x(3)and en; --0010
OUT0<=x(0)and a(1)and x(2)and x(3)and en; --0100
NOP<=x(0)and a(1)and a(2)and a(3)and x(4)and x(5)and x(6)and x(7)and en; --01110000
HALT<=a(0)and x (1)and x(2)and x(3)and x(4)and x(5)and x(6)and x(7)and en; --10000000
end aaa;