阻塞vs非阻塞

= , <=

module zuse(clk,a1,c1,a2,c2);
input clk;
input a1;
input a2;
output c1;
output c2;
reg b1;
reg b2;
reg c1;
reg c2;

always @ (posedge clk) begin
 b1=a1;
 c1=b1;
end
always @ (posedge clk) begin
 b2<=a2;
 c2<=b2;
end

endmodule

结果