Quartus手动生成波形图(以38译码器为例)VHDL
1.新建工程输入代码并运行LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY dcd_38 IS PORT(A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); --输入端 LED8S1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --输出端END dcd_38;ARCHITECTURE behave OF dcd_38 IS --实现CASE语句BEGI
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2022-05-03 11:36:54 ·
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