Quartus手动生成波形图（以38译码器为例）VHDL

1.新建工程输入代码并运行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dcd_38 IS
	PORT(A:IN STD_LOGIC_VECTOR(2 DOWNTO 0);               --输入端
		  LED8S1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));  --输出端
END dcd_38;

ARCHITECTURE behave OF dcd_38 IS      --实现CASE语句
BEGIN
PROCESS(A)                           --顺序执行
BEGIN
CASE A IS
WHEN "000" =>LED8S1<="11111110";
WHEN "001" =>LED8S1<="11111101";
WHEN "010" =>LED8S1<="11111011";
WHEN "011" =>LED8S1<="11110111";
WHEN "100" =>LED8S1<="11101111";
WHEN "101" =>LED8S1<="11011111";
WHEN "110" =>LED8S1<="10111111";
WHEN "111" =>LED8S1<="01111111";
WHEN OTHERS=>NULL;                    
END CASE;
END PROCESS;
END behave;