合工大计算机体系结构 头歌作业 多路选择器基础版

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---

assign Y=(sel==3'b000)?D[0]:(sel==3'b001)?D[1]:(sel==3'b010)?D[2]:(sel==3'b011)?D[3]:(sel==3'b100)?D[4]:(sel==3'b101)?D[5]:(sel==3'b110)?D[6]:(sel==3'b110)?D[6]:D[7];

---

  reg Y;

always @(*) begin

if (sel==3'b000)

    Y=D[0];

else if(sel==3'b001)

    Y=D[1];

else if(sel==3'b010)

    Y=D[2];

else if(sel==3'b011)

    Y=D[3];

else if(sel==3'b100)

    Y=D[4];

else if(sel==3'b101)

    Y=D[5];

else if(sel==3'b110)

    Y=D[6];

else if(sel==3'b111)

    Y=D[7];

end

 

---

reg Y;

always @(*) begin

case(sel)

    3'b001:Y=D[1];

    3'b000:Y=D[0];

    3'b010:Y=D[2];

    3'b011:Y=D[3];

    3'b100:Y=D[4];

    3'b101:Y=D[5];

    3'b110:Y=D[6];

    3'b111:Y=D[7];

endcase

end

---

wire a,b;

mux2 c1(D[1:0],sel[0],a);

mux2 c2(D[3:2],sel[0],b);

assign Y=(sel[1]==1)?b:a;

---

reg Y;

always @(*) begin

case(sel)

    3'b000:Y=D0;

    3'b001:Y=D1;

    3'b010:Y=D2;

    3'b011:Y=D3;

    3'b100:Y=D4;

    3'b101:Y=D5;

    3'b110:Y=D6;

    3'b111:Y=D7;

    endcase

end

---

reg [3:0]Y;

    always @(*) begin

    case(sel)

    4'b0000:Y=D0;

    4'b0001:Y=D1;

    4'b0010:Y=D2;

    4'b0011:Y=D3;

    4'b0100:Y=D4;

    4'b0101:Y=D5;

    4'b0110:Y=D6;

    4'b0111:Y=D7;

    4'b1000:Y=D8;

    default:

    Y=4'hF;

    endcase

end

 

---

reg Y;

integer i;

always @(*) begin

for(i=0;i<=255;i=i+1)

    if(sel==i) Y=D[i];

end

 

---

assign Y={D[4*sel+4],D[4*sel+3],D[4*sel+2],D[4*sel+1],D[4*sel]};

---

    assign out = ({8{sel}} & a) | ({8{~sel}} & b);

---

    wire [7:0]out0, out1;        // 相当于SystemVerilog中“logic out0, out1;”

    mux2 mux0 ( sel[0],    a,    b, out0 );

    mux2 mux1 ( sel[0],    c,    d, out1 );

    mux2 mux2 ( sel[1], out0, out1,  out );

---

always @(*) begin

    valid=1;

    out=0;

        case (code)

            8'h45: out = 0;

            8'h16: out = 1;

            8'h1e: out = 2;

            8'h26: out = 3;

            8'h25: out = 4;

            8'h2e: out = 5;

            8'h36: out = 6;

            8'h3d: out = 7;

            8'h3e: out = 8;

            8'h46: out = 9;

            default: valid = 0;

        endcase

    end