qqmax100的专栏

原创 Java内存区域与内存溢出异常

原创 测试

library ieee;use ieee.std_logic_1164.all;package analog_pack is type analog_io_ut is record ani : integer; ano : real; end record;end analog_pack;use work.analog_pack.all;entity en

原创 代码高亮

Verilog package: snps_vlog_packagetypedef struct { real v[3:1]; /* Unpacked real array */ logic active;} v_wireT; function automatic v_wireT v_wire_rf(input v_wireT drive