代码高亮

Verilog package: snps_vlog_package
typedef struct {
        real  v[3:1];    /* Unpacked real array */
        logic active;
} v_wireT;
 
function v_wireT v_wire_rf(input v_wireT driver[]);  /* Resolution function */
nettype v_wireT  v_wire_avg  with v_wire_rf;

 

VHDL package: snps_vhdl_package
type real_vec is array (3 downto 1) of real;
type vh_uwire is record
        v:           real_vec;
        active:   std_ulogic;
end record;
 
type vh_uwire_vector is array (natural range <>) of vh_uwire;
function resolved_average (s: vh_uwire_vector) return vh_uwire;  --- Resolution function
subtype vh_wire_avg is resolved_average vh_uwire;

 

library ieee;
use ieee.std_logic_1164.all;

package analog_pack is
  type analog_io_ut is record
    ani : integer;
    ano : real;
  end record;
end analog_pack;

use work.analog_pack.all;

entity en is
end en;

architecture ar of en is
begin
end ar;