更详细的内容请看
手册中第三卷中的2.5 CONTROL REGISTERS
更多参考
《软件调试第二版:卷1硬件基础》 中的第2.44章 控制寄存器
控制寄存器
描述:
控制寄存器有五个,分别是:Cr0 Cr1 Cr2 Cr3 和Cr4,在64位模式下还有个Cr8
Control registers (CR0, CR1, CR2, CR3, and CR4; see Figure 2-7)
Register CR8 is available in 64-bit mode only.
控制寄存器的作用:
确定处理器的工作模式
其中
Cr1是保留的
Cr3我们大家都知道,保存的是页目录表基址和两个标志位(PCD和PWT)
CR1 — Reserved.
CR3 — Contains the physical address of the base of the paging-structure hierarchy and two flags (PCD and
PWT). Only the most-significant bits (less the lower 12 bits) of the base address are specified; the lower 12 bits
of the address are assumed to be 0. The first paging structure must thus be aligned to a page (4-KByte)
boundary. The PCD and PWT flags control caching of that paging structure in the processor’s internal data
caches (they do not control TLB caching of page-directory information).
When using the physical address extension, the CR3 register contains the base address of the page-directorypointer table In IA-32e mode, the CR3 register contains the base address of the PML4 table.
See also: Chapter 4, “Paging.”
Cr0
描述:
CR0 — Contains system control flags that control operating mode and states of the processor.
结构图:
PE
位:启用保护(Protecction Enable)标志
PE
=1:保护模式
PE
=0:实地址模式
这个标志仅开启段级保护,而没有启用分页机制
若要启用分页机制,那么PE
和PG
标志都要置位
PG
位:分页机制标志
PG
=1:开启了分页机制
PG
=0:未开启分页机制
在开启这个标志位之前必须已经或者同时开启PE标志
PG
=0且PE
=0:处理器工作状态为实地址模式
PG
=0且PE
=1:处理器工作状态为没有开启分页机制的保护模式
PG
=1且PE
=0:不存在。在PE没有开启的情况下无法开启PG
PG
=1且PE
=1:处理器工作状态为开启了分页机制的保护模式
WP
位:写保护(Write Proctect)标志
对于Intel 80486或以上的CPU,Cr0
的16位是写保护标志
当设置该标志时,处理器会禁止超级用户程序(例如特权级0的程序)向用户级只读页面执行写操作
当CPL
<3的时候:
如果 WP
=0 可以读写任意用户级物理页,只要线性地址有效
如果 WP=
1 可以读取任意用户级物理页,但对于只读的物理页,则不能写
PG - Paging (bit 31 of CR0) — Enables paging when set; disables paging when clear. When paging is
disabled, all linear addresses are treated as physical addresses. The PG flag has no effect if the PE flag (bit
0 of register CR0) is not also set; setting the PG flag when the PE flag is clear causes a general-protection
exception (#GP). See also: Chapter 4, “Paging.”
WP - Write Protect (bit 16 of CR0) — When set, inhibits supervisor-level procedures from writing into readonly pages; when clear, allows supervisor-level procedures to write into read-only pages (regardless of the
U/S bit setting; see Section 4.1.3 and Section 4.6). This flag facilitates implementation of the copy-onwrite method of creating a new process (forking) used by operating systems such as UNIX.
PE - Protection Enable (bit 0 of CR0) — Enables protected mode when set; enables real-address mode when
clear. This flag does not enable paging directly. It only enables segment-level protection. To enable paging,
both the PE and PG flags must be set.
这里只简单介绍几个标志位,如果对其他位感兴趣可以去手册里看更详细的解释
Cr2
描述:
当CPU访问某个无效页面时,会产生缺页异常,此时,CPU会将引起异常的线性地址存放在CR2中
CR2 — Contains the page-fault linear address (the linear address that caused a page fault)
结构图:
举例:
- 当CPU访问某个物理页,但PDE/PTE的P位为0时,会产生缺页异常
- 缺页异常一旦发生,CPU会将引起缺页异常的线性地址存储到Cr2中
- 此时,操作系统的处理程序开始对异常进行处理
- 若处理结束后,虽然PDE/PTE的P位为0,但实际上它被写进了页面
- 这时,处理程序会将数据从页面中读出,再挂上一个有效的物理页,让程序接着往下跑
- 程序往下跑时,操作系统必须要记录程序原先已经跑到了哪里
- 此时,Cr2便派上了用场,因为产生异常时的线性地址存在了Cr2中
- 但如果异常处理程序检测到用户访问的页面是一个未分配的页面
- 这时,操作系统会报告一个异常,告诉我们在哪里发生了错误
- 若没有Cr2寄存器,当进入异常处理程序时,将找不到回去的线性地址
Cr4
描述:
CR4 — Contains a group of flags that enable several architectural extensions, and indicate operating system or
executive support for specific processor capabilities. The control registers can be read and loaded (or modified)
using the move-to-or-from-control-registers forms of the MOV instruction. In protected mode, the MOV
instructions allow the control registers to be read or loaded (at privilege level 0 only). This restriction means
that application programs or operating-system procedures (running at privilege levels 1, 2, or 3) are prevented
from reading or loading the control registers.
结构图:
PAE
:
PAE
=1:2-9-9-12分页
PAE
=0:10-10-12分页
PSE
:
PSE=1
10-10-12 PS=1 4M页 2-9-9-12 PS=1 2M页
PS=0 4K页 PS=0 4K页
PSE=0
10-10-12 PS=1 4K页 2-9-9-12 PS=1 4K页
PS=0 4K页 PS=0 4K页
SMEP
(Supervisor Mode Execution Prevention),管理模式执行保护)的作用分别是禁止内核CPU访问用户空间的数据和执行用户空间的代码,并不会因为你权限高就能访问/执行低权限的资源,你的就是你的,我的就是我的,而之前零环权限就很牛逼了,你的就是我的,我的还是我的.
简单来说,它是内核的一种保护机制,作用是当CPU处于ring0模式的时候,如果执行了用户空间的代码就会触发页错误,很明现这个保护机制就是为了防止ret2usr攻击的
详情请看:
https://bbs.pediy.com/thread-261744.htm
PAE - Physical Address Extension (bit 5 of CR4) — When set, enables paging to produce physical addresses
with more than 32 bits. When clear, restricts physical addresses to 32 bits. PAE must be set before entering
IA-32e mode.
PSE - Page Size Extensions (bit 4 of CR4) — Enables 4-MByte pages with 32-bit paging when set; restricts
32-bit paging to pages to 4 KBytes when clear.
SMEP
SMEP-Enable Bit (bit 20 of CR4) — Enables supervisor-mode execution prevention (SMEP) when set.
See Section 4.6, “Access Rights”.
《软件调试第二版:卷1硬件基础》中的解释
图2-2控制寄存器中的标志位
mov Crn
命令用来读写控制寄存器的内容,只有在0特权级才能执行这个指令。
关于控制寄存器的更多细节
可以在开头就提到的手册中第三卷中的2.5 CONTROL REGISTERS
不同版本的手册对应的具体目录可能不同,但是标题基本不会变,直接搜索标题关键字即可找到