usb to ethernet adapter (moshi) work in linux kernel

1. driver position

drivers/net/usb

Makefile:

        obj-$(CONFIG_USB_NET_AX8817X)   += asix.o

Config:

#
# USB Network Adapters
#
CONFIG_USB_USBNET=y
CONFIG_USB_NET_AX8817X=y
CONFIG_USB_NET_CDCETHER=y
CONFIG_USB_NET_CDC_EEM=y
CONFIG_USB_NET_CDC_NCM=y
CONFIG_USB_NET_SMSC95XX=y
CONFIG_USB_NET_NET1080=y
CONFIG_USB_NET_MCS7830=y
CONFIG_USB_NET_RNDIS_HOST=y
CONFIG_USB_NET_CDC_SUBSET=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_NET_ZAURUS=y

2. chip

AX88772 -- 內建PHY之USB2.0高速乙太網路控制晶片

The AX88772 USB to 10/100 Fast Ethernet/HomePNA/HomePlug controller is a high performance and highly integrated ASIC with embedded 28KB SRAM for packet buffering. It enables low cost and affordable Fast Ethernet network connection to desktop, notebook PC, and embedded system using popular USB ports. It has an USB interface to communicate with USB host controller and is compliant with USB specification V1.0, V1.1 and V2.0. It implements 10/100Mbps Ethernet LAN function based on IEEE802.3, and IEEE802.3u standards or HomePNA standard. It integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design and provides an optional media-independent interface (MII) for implementing Fast Ethernet and HomePNA functions.  規格: Single chip USB to 10/100 Fast Ethernet and HomePNA and HomePlug Network Controller. Integrates on-chip 10/100Mbps Fast Ethernet PHY. USB specification 1.0 and 1.1 and 2.0 compliant. Supports USB Full and High Speed modes with Bus power capability. Supports 4 endpoints on USB interface. High performance packet transfer rate over USB bus using proprietary burst transfer mechanism (US Patent Approval). IEEE 802.3 10BASE-T and 100BASE-TX compatible. Embedded 20KB SRAM for RX packet buffering and 8KB SRAM for TX packet buffering. Supports both full-duplex and half-duplex operation on Fast Ethernet. Provide optional MII interfaces for Ethernet PHY and HomePNA/HomePlug PHY interface. Supports suspend mode and remote wakeup via link-up, magic packet, or external pin. Optional PHY power down during suspend mode. Supports 256/512 bytes (93c56/93c66) of serial EEPROM (for storing USB Descriptors). Supports automatic loading of Ethernet ID, USB Descriptors and Adapter Configuration from EEPROM after power-on initialization.initialization. External PHY loop-back diagnostic capability. Integrates on-chip 3.3V to 2.5V voltage regulator and requires only single power supply: 3.3V. Small form factor with 128-pin LQFP package. 12MHz and 25MHz clock input from either crystal or oscillator source.