老师布置的任务，做实验实现dlx指令集的一个5级pipeline的cpu。
那天晚上，为了处理流水线的相关问题，搞了半夜，复制粘贴了3k多行代码，搞的头昏眼花的，
不过终究算是通过了，相关处理的很顺利，cpu也基本搞定，
后来又添加了跳转指令成功时的流水线排空操作，
cpu也算大功告成了。
支持add、addi、ld、sw 4条指令，哈佛结构
目前未发现bug，
现在拿出来和大家分享，希望能与有相同爱好的同志多交流
对于相关问题的解决方案是最简单的暂停流水线
跳转时流水线的处理方式是：排空流水线
操作码格式：
11xxxx://R类指令
01xxxx: //I 类指令
0110xx://I 类指令& 操作ALU
0101xx://I类指令 & 写存储器
0100xx://I类指令 & 读存储器
0111xx://I类指令 & 实现跳转
011100://I类指令 & bnez
011101://I类指令 & beqz
具体指令格式请参考dlx指令系统。
http://www.csee.umbc.edu/courses/undergraduate/411/spring96/dlx.html
cpu实现文件（dlx.v）
// ***************************************************************************
// ** Copyright (c) 2008-2011 Embedded System Lab, USTC. **
// ** All rights reserved. **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: dlx.v
// Version: 1.00
// Description: DLX pipelined cpu design
//----------------------------------------------------------------------------
module dlx
(
iClk,
iRst,
//memory
oWe_mem,
orAddr_mem,
owAddr_mem,
iData_mem,
oData_mem,
//ram
oWe_ram,
orAddr_ram,
owAddr_ram,
iData_ram,
oData_ram
);
input iClk;
input iRst;
//memory
output oWe_mem;
output [0:6] orAddr_mem;
output [0:6] owAddr_mem;
input [0:31] iData_mem;
output [0:31] oData_mem;
//ram
output oWe_ram;
output [0:6] orAddr_ram;
output [0:6] owAddr_ram;
input [0:31] iData_ram;
output [0:31] oData_ram;
//regfile
wire oWe_reg;
wire [0:4] orAddr_reg_A;
wire [0:4] orAddr_reg_B;
wire [0:4] owAddr_reg;
wire [0:31] iData_reg_A;
wire [0:31] iData_reg_B;
wire [0:31] oData_reg;
regfile reg_file_ins(.iClk(iClk),
.iRst(iRst),
.iWe(oWe_reg),
.iwAddr(owAddr_reg),
.iData(oData_reg),
.irAddr_A(orAddr_reg_A),
.irAddr_B(orAddr_reg_B),
.oData_A(iData_reg_A),
.oData_B(iData_reg_B));
/************************IF stage******************************/
reg [0:31] IF_IR;
reg [0:31] PC;
//deals are at the bottom of this file
//confict delay
//IF stage NPC transforms
reg [0:31] IF_NPC;
always @(posedge iClk)
if(iRst)
IF_NPC<=64;
else
IF_NPC <= PC + 32'd1 ;
//Read address of memory for instruction
assign orAddr_mem = PC[25:31] ;
/************************ID stage*****************************/
reg EX_Cond;
//ID stage NPC transforms
reg [0:31] ID_NPC;
always @(posedge iClk)
if(iRst)
ID_NPC <= 32'd65;
else
ID_NPC <= IF_NPC ;
//IF stage IF_IR transforms
reg [0:31] ID_IR;
always @(posedge iClk)
if(iRst)
ID_IR <= 32'b0;
else
ID_IR<= EX_Cond ? 32'b0 : IF_IR ;
//ID stage ID_A transforms
reg [0:31] ID_A;
always @(posedge iClk)
if(iRst)
ID_A <= 32'b0;
else
ID_A <= iData_reg_A;
assign orAddr_reg_A = IF_IR[6:10] ;
//ID stage ID_B transforms
reg [0:31] ID_B;
always @(posedge iClk)
if(iRst)
ID_B <= 32'b0;
else
ID_B <= iData_reg_B;
assign orAddr_reg_B = IF_IR[11:15];
//Immediate operand generates and only uses in the next stage
//wire [0:31] ID_Imm;
//assign ID_Imm = {{16{IF_IR[16]}},IF_IR[16:31]};
reg [0:31] ID_Imm;
always @(posedge iClk)
if(iRst)
ID_Imm = 32'b0;
else
ID_Imm <= {{16{IF_IR[16]}},IF_IR[16:31]};
/************************EX stage*****************************/
/*
at this stage calculate EX_cond / EX_AluOutput
*/
//EX stage EX_IR transforms
reg [0:31] EX_IR;
always @(posedge iClk)
if(iRst)
EX_IR <= 32'b0;
else
EX_IR <= EX_Cond ? 32'b0 : ID_IR ;
//EX stage EX_B transforms
reg [0:31] EX_B;
always @(posedge iClk)
if(iRst)
EX_B <= 32'b0;
else
EX_B <= ID_B;
//EX stage cond transforms
//reg EX_Cond; // declared before
always @(posedge iClk)
if(iRst)
EX_Cond <= 1'b0;
else
casex(ID_IR[0:5])
6'b11xxxx://R class instruction
EX_Cond <= 1'b0;
6'b0110xx://I class & operates ALU
EX_Cond <= 1'b0;
6'b011100://I class & Jump nez
EX_Cond <= |ID_A ; //decrease bit operation
6'b011101://I class & Jump ez
EX_Cond <= ~(|ID_A) ; //decrease bit operation
6'b010xxx://I class & accesses memory
EX_Cond <= 1'b0;
6'b10xxxx://J class instruction
EX_Cond <= 1'b0;
default:
EX_Cond <= 1'b0;
endcase
//EX stage EX_AluOutput transforms
reg [0:31] EX_AluOutput;
always @(posedge iClk)
if(iRst)
EX_AluOutput <= 32'b0 ;
else
casex(ID_IR[0:5])
6'b11xxxx://R class instruction
casex(ID_IR[21:31])
11'b00000000001:// add
EX_AluOutput <= ID_A + ID_B ;
default:
EX_AluOutput <= 32'bz ;
endcase
6'b0110xx://I class & operates ALU
casex(ID_IR[0:5])
6'bxxx001://addi
EX_AluOutput <= ID_A + ID_Imm ;
default:
EX_AluOutput <= 32'bz;
endcase
6'b010xxx://I class & accesses memory
EX_AluOutput <= ID_A + ID_Imm ;
6'b0111xx://I class & Jump
EX_AluOutput <= ID_NPC + ID_Imm ;
6'b10xxxx://J class instruction
EX_AluOutput <= ID_NPC + ID_Imm ;
default:
EX_AluOutput <= 32'bz ;
endcase
/************************MEM stage*****************************/
//MEM stage MEM_IR transforms
reg [0:31] MEM_IR;
always @(posedge iClk)
if(iRst)
MEM_IR <= 32'b0;
else
MEM_IR <= EX_Cond ? 32'b0 : EX_IR ;
//MEM stage MEM_AluOutput transforms
reg [0:31] MEM_AluOutput;
always @(posedge iClk)
if(iRst)
MEM_AluOutput <= 32'b0 ;
else
casex(EX_IR[0:5])
6'b11xxxx://R class instruction
MEM_AluOutput <= EX_AluOutput ;
6'b011xxx://I class & operates ALU
MEM_AluOutput <= EX_AluOutput ;
default:
MEM_AluOutput <= 32'bz ;
endcase
//MEM stage MEM_oData_ram transforms
reg [0:31] MEM_oData_ram;
always @(posedge iClk)
if(iRst)
MEM_oData_ram <= 32'b0 ;
else
casex(EX_IR[0:5])
6'b0101xx://I class & write memory
MEM_oData_ram <= EX_B ;
default:
MEM_oData_ram <= 32'bz ;
endcase
assign oData_ram = MEM_oData_ram;
//MEM stage MEM_oWe_ram transforms
reg MEM_oWe_ram;
always @(posedge iClk)
if(iRst)
MEM_oWe_ram <= 1'b0 ;
else
casex(EX_IR[0:5])
6'b0101xx://I class & write memory
MEM_oWe_ram <= 1'b1 ;
default:
MEM_oWe_ram <= 1'b0 ;
endcase
assign oWe_ram = MEM_oWe_ram;
//iData_ram is fetched in this cycle
//but MEM_LMD will be used in the next cycle
//so, we use a wire instead of a register....
wire [0:31] MEM_LMD;
assign MEM_LMD = iData_ram;
//MEM stage MEM_orAddr_ram transforms
reg [0:6] MEM_orAddr_ram;
always @(posedge iClk)
if(iRst)
MEM_orAddr_ram <= 7'b0 ;
else
casex(EX_IR[0:5])
6'b0100xx://I class & read memory
MEM_orAddr_ram <= EX_AluOutput[25:31] ;
default:
MEM_orAddr_ram <= 7'bz;
endcase
assign orAddr_ram = MEM_orAddr_ram ;
//MEM stage MEM_oWe_ram transforms
reg [0:6] MEM_owAddr_ram ;
always @(posedge iClk)
if(iRst)
MEM_owAddr_ram <= 7'b0 ;
else
casex(EX_IR[0:5])
6'b0101xx://I class & write memory
MEM_owAddr_ram <= EX_AluOutput[25:31] ;
default:
MEM_owAddr_ram <= 7'bz ;
endcase
assign owAddr_ram = MEM_owAddr_ram ;
/************************WB stage*****************************/
//WB stage WB_owAddr_reg transforms
reg [0:4] WB_owAddr_reg;
always @(posedge iClk)
if(iRst)
WB_owAddr_reg <= 5'b0 ;
else
casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
WB_owAddr_reg <= MEM_IR[16:20] ;
6'b0110xx://I class & operates ALU
WB_owAddr_reg <= MEM_IR[11:15] ;
6'b0100xx://I class & read memory
WB_owAddr_reg <= MEM_IR[11:15] ;
default:
WB_owAddr_reg <= 5'bz ;
endcase
assign owAddr_reg = WB_owAddr_reg;
//WB stage WB_oWe_reg transforms
reg WB_oWe_reg;
always @(posedge iClk)
if(iRst)
WB_oWe_reg <= 1'b0 ;
else
casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
WB_oWe_reg <= 1'b1 ;
6'b0110xx://I class & operates ALU
WB_oWe_reg <= 1'b1 ;
6'b0100xx://I class & read memory
WB_oWe_reg <= 1'b1 ;
default:
WB_oWe_reg <= 1'b0 ;
endcase
assign oWe_reg = WB_oWe_reg ;
//WB stage WB_oData_reg transforms
reg [0:31] WB_oData_reg;
always @(posedge iClk)
if(iRst)
WB_oData_reg <= 32'b0 ;
else
casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
WB_oData_reg <= MEM_AluOutput ;
6'b0110xx://I class & operates ALU
WB_oData_reg <= MEM_AluOutput ;
6'b0100xx://I class & read memory
WB_oData_reg <= MEM_LMD ;
default:
WB_oData_reg <= 32'bz ;
endcase
assign oData_reg = WB_oData_reg ;
/************************Confilict dealing*****************************/
//change normal IF_IR inc
always @(posedge iClk)
if(iRst)
IF_IR<= 32'd0;
else
casex(iData_mem[0:5])//current instruction fetching ...
6'b11xxxx://R class instruction
casex(IF_IR[0:5])
//casex(IF_IR[0:5])
6'b11xxxx://R class instruction
//casex(IF_IR[0:5])
if(IF_IR[16:20] == iData_mem[6:10] || IF_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] || ID_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] || ID_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(EX_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
6'b01xxxx: //I class
//casex(IF_IR[0:5])
if(IF_IR[11:15] == iData_mem[6:10] || IF_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] || ID_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] || ID_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
default:
//casex(IF_IR[0:5])
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] || ID_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] || ID_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
endcase
//casex(IF_IR[0:5])
6'b11xxxx://I class
// casex(iData_mem[0:5])
casex(IF_IR[0:5])
6'b11xxxx: //R class instruction
if(iData_mem[6:10] == IF_IR[16:20])
PC <= PC;
else
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
6'b01xxxx: //I class
//casex(IF_IR[0:5])
if(iData_mem[6:10] == IF_IR[11:15])
PC <= PC;
else
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem ;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
default:
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
IF_IR<= 32'd0 ;
else
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
default:
//casex(MEM_IR[0:5])
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
endcase
default://current instruction doesn't use registers, skip...
IF_IR<= EX_Cond ? 32'b0 : iData_mem;
endcase//casex(iData_mem[0:5])
/************************Confilict dealing*****************************/
//change normal PC inc
always @(posedge iClk)
if(iRst)
PC<=32'd64;
else
casex(iData_mem[0:5])//current instruction fetching ...
6'b11xxxx://R class instruction
casex(IF_IR[0:5])
//casex(IF_IR[0:5])
6'b11xxxx://R class instruction
//casex(IF_IR[0:5])
if(IF_IR[16:20] == iData_mem[6:10] || IF_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] || ID_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] || ID_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(EX_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
6'b01xxxx: //I class
//casex(IF_IR[0:5])
if(IF_IR[11:15] == iData_mem[6:10] || IF_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] || ID_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] || ID_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
default:
//casex(IF_IR[0:5])
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] || ID_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] || ID_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] || EX_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] || EX_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] || MEM_IR[16:20]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] || MEM_IR[11:15]==iData_mem[11:15])
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
endcase
//casex(IF_IR[0:5])
6'b11xxxx://I class
// casex(iData_mem[0:5])
casex(IF_IR[0:5])
6'b11xxxx: //R class instruction
if(iData_mem[6:10] == IF_IR[16:20])
PC <= PC;
else
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
6'b01xxxx: //I class
//casex(IF_IR[0:5])
if(iData_mem[6:10] == IF_IR[11:15])
PC <= PC;
else
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
default:
casex(ID_IR[0:5])
//casex(ID_IR[0:5])
6'b11xxxx://R class instruction
//casex(ID_IR[0:5])
if(ID_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
6'b01xxxx: //I class
//casex(ID_IR[0:5])
if(ID_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
default:
//casex(ID_IR[0:5])
casex(EX_IR[0:5])
//casex(EX_IR[0:5])
6'b11xxxx://R class instruction
//casex(EX_IR[0:5])
if(EX_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
6'b01xxxx: //I class
//casex(EX_IR[0:5])
if(EX_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
default:
//casex(EX_IR[0:5])
casex(MEM_IR[0:5])
//casex(MEM_IR[0:5])
6'b11xxxx://R class instruction
//casex(MEM_IR[0:5])
if(MEM_IR[16:20] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
6'b01xxxx: //I class
//casex(MEM_IR[0:5])
if(MEM_IR[11:15] == iData_mem[6:10] )
PC<= PC ;
else
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
default:
//casex(MEM_IR[0:5])
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase
//casex(MEM_IR[0:5])
endcase
//casex(EX_IR[0:5])
endcase
//casex(ID_IR[0:5])
endcase
default://current instruction doesn't use registers, skip...
PC<= EX_Cond ? EX_AluOutput : PC + 32'd1;
endcase//casex(iData_mem[0:5])
/*****************end of Confilict dealing*************************/
endmodule
寄存器文件regfile.v
// ***************************************************************************
// ** Copyright (c) 2008-2011 Embedded System Lab, USTC. **
// ** All rights reserved. **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: regfile.v
// Version: 1.00
// Description: a verilog register file design
// Date: 12/9/2011
// Author: Junneng Zhang
//----------------------------------------------------------------------------
module regfile
(
iClk,
iRst,
//write
iWe,
iwAddr,
iData,
//read
irAddr_A,
irAddr_B,
oData_A,
oData_B
);
input iClk;
input iRst;
//write
input iWe;
input [0:4] iwAddr;
input [0:31] iData;
//read
input [0:4] irAddr_A;
input [0:4] irAddr_B;
output [0:31] oData_A;
output [0:31] oData_B;
reg [0:31] reg_file [0:31];
assign oData_A = reg_file[irAddr_A];
assign oData_B = reg_file[irAddr_B];
always @(posedge iClk)
begin
if(iRst)
begin
reg_file[0] = 0;
reg_file[1] = 1;
reg_file[2] = 2;
reg_file[3] = 3;
reg_file[4] = 4;
reg_file[5] = 5;
reg_file[6] = 6;
reg_file[7] = 7;
reg_file[8] = 8;
reg_file[9] = 9;
reg_file[10] = 10;
reg_file[11] = 11;
reg_file[12] = 12;
reg_file[13] = 13;
reg_file[14] = 14;
reg_file[15] = 15;
end
else if(iWe)
begin
reg_file[iwAddr] = iData;
end
end
endmodule
存储器文件 memory.v
// ***************************************************************************
// ** Copyright (c) 2008-2011 Embedded System Lab, USTC. **
// ** All rights reserved. **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: memory.v
// Version: 1.00
// Description: a verilog memory design
// Date: 12/9/2011
// Author: Junneng Zhang
//----------------------------------------------------------------------------
module memory
(
iClk,
iRst,
iWe,
irAddr,
iwAddr,
iData,
oData
);
input iClk;
input iRst;
input iWe;
input [0:6] irAddr;
input [0:6] iwAddr;
input [0:31] iData;
output [0:31] oData;
reg [0:31] mem [0:127];
assign oData = mem[irAddr];
always @(posedge iClk)
begin
if(iRst)
begin
mem[0]=32'd4; // data
mem[7]=32'd1989;// data
mem[8]=32'd2012;// data
mem[64]=32'b010000_00000_00001_00000000_00000111;//lw r1,7(r0) ;r1 = [r0+7] = [7] = 1989
mem[65]=32'b010000_00000_00010_00000000_00001000;//lw r2,8(r0) ;r2 = [r0+8] = [8] = 2012
mem[66]=32'b110000_00101_00010_00101_00000000001;//add r5,r5,r2 ;r5 = r5+r2 = 2017
mem[67]=32'b010100_00000_00100_00000000_00000100;//sw 4,r4 ;[4] = r4 = 4
mem[68]=32'b011001_00000_00001_00000000_00000001;//addi r1,1(r0);r1 = r0 + 1 = 1
mem[69]=32'b011101_00001_00000_00000000_00010000;//jez r1,16 ;no jump
mem[70]=32'b011100_00001_00000_00000000_00010000;//jnez r1,16 ;jump to 70 + 16
mem[71]=32'b110000_00101_00010_00101_00000000001;//add r5,r5,r2 ;r5 = r5+r2 = 4029 && not execute!!!!
mem[72]=32'b110000_00100_00010_00100_00000000001;//add r4,r4,r2 ;r4 = r4+r2 = 2016 && not execute!!!!
mem[73]=32'b110000_00110_00010_00110_00000000001;//add r6,r6,r2 ;r6 = r6+r2 = 2018 && not execute!!!!
mem[74]=32'b0;//nop
mem[71+16]=32'b110000_00001_00010_00010_00000000001;//add r2,r2,r1 ;r2 = r2 + r1 = 2012 + 1 = 2013
mem[72+16]=32'b110000_00011_00010_00100_00000000001;//add r4,r3,r2 ;r4 = r3 + r2 = 3 + 2013 = 2016
mem[73+16]=32'b0;
mem[74+16]=32'b0;
end
else if(iWe)
begin
mem[iwAddr] = iData;
end
else
begin
end
end
endmodule
测试 向量testbench.v
module test;
reg clk;
reg rst;
wire oWe_mem;
wire [0:6] orAddr_mem;
wire [0:6] owAddr_mem;
wire [0:31] iData_mem;
wire [0:31] oData_mem;
wire oWe_ram;
wire [0:6] orAddr_ram;
wire [0:6] owAddr_ram;
wire [0:31] iData_ram;
wire [0:31] oData_ram;
dlx cpu(.iClk(clk),
.iRst(rst),
.oWe_mem(oWe_mem),
.orAddr_mem(orAddr_mem),
.owAddr_mem(owAddr_mem),
.iData_mem(iData_mem),
.oData_mem(oData_mem),
.oWe_ram(oWe_ram),
.orAddr_ram(orAddr_ram),
.owAddr_ram(owAddr_ram),
.iData_ram(iData_ram),
.oData_ram(oData_ram));
memory flash(.iClk(clk),
.iRst(rst),
.iWe(oWe_mem),
.irAddr(orAddr_mem),
.iwAddr(owAddr_mem),
.iData(oData_mem),
.oData(iData_mem));
memory ram(.iClk(clk),
.iRst(rst),
.iWe(oWe_ram),
.irAddr(orAddr_ram),
.iwAddr(owAddr_ram),
.iData(oData_ram),
.oData(iData_ram));
always #10 clk = ~clk;
initial
begin
clk = 0;
rst = 1;
#20 rst = 0;
end
endmodule
modelsim仿真激励文件tb.do
vlog regfile.v memory.v dlx.v testbench.v
vsim work.test
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix unsigned /test/flash/mem
add wave -noupdate -radix unsigned /test/ram/mem
add wave -noupdate -radix unsigned /test/cpu/reg_file_ins/reg_file
add wave -noupdate -radix unsigned /test/cpu/iClk
add wave -noupdate -radix unsigned /test/cpu/iRst
add wave -noupdate -radix unsigned /test/cpu/IF_IR
add wave -noupdate -radix unsigned /test/cpu/ID_IR
add wave -noupdate -radix unsigned /test/cpu/EX_IR
add wave -noupdate -radix unsigned /test/cpu/MEM_IR
add wave -noupdate -radix unsigned /test/cpu/IF_NPC
add wave -noupdate -radix unsigned /test/cpu/PC
add wave -noupdate -radix unsigned /test/cpu/EX_Cond
add wave -noupdate -radix unsigned /test/cpu/EX_AluOutput
add wave -noupdate -radix unsigned /test/cpu/ID_NPC
add wave -noupdate -radix unsigned /test/cpu/ID_A
add wave -noupdate -radix unsigned /test/cpu/ID_B
add wave -noupdate -radix unsigned /test/cpu/ID_Imm
add wave -noupdate -radix unsigned /test/cpu/EX_B
add wave -noupdate -radix unsigned /test/cpu/MEM_AluOutput
add wave -noupdate -radix unsigned /test/cpu/MEM_oData_ram
add wave -noupdate -radix unsigned /test/cpu/MEM_oWe_ram
add wave -noupdate -radix unsigned /test/cpu/MEM_LMD
add wave -noupdate -radix unsigned /test/cpu/MEM_orAddr_ram
add wave -noupdate -radix unsigned /test/cpu/MEM_owAddr_ram
add wave -noupdate -radix unsigned /test/cpu/WB_owAddr_reg
add wave -noupdate -radix unsigned /test/cpu/WB_oWe_reg
add wave -noupdate -radix unsigned /test/cpu/WB_oData_reg
TreeUpdate [SetDefaultTree]
configure wave -namecolwidth 191
configure wave -valuecolwidth 40
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {630 ns}
run 600仿真波形：
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